Datasheet ADA4098-1 (Analog Devices) - 3

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Preliminary Technical Data ADA4098-1 SPECIFICATIONS 5 V SUPPLY
Common-mode voltage (VCM) = 2.5 V, SHDN pin is open, load resistance (RL) = 499 kΩ to midsupply, ambient temperature (TA) = 25°C, unless otherwise noted.
Table 1. B Grade H-Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
DC PERFORMANCE Offset Voltage (VOS)1 0.25 V < VCM < 3.5 V ±15 ±30 ±15 ±30 µV Minimum temperature (TMIN) < TA ±90 ±100 µV < maximum temperature (TMAX) 0.25 V < VCM < 70 V ±20 ±40 ±20 ±40 µV TMIN < TA < TMAX ±100 ±110 µV −0.1 V < VCM < +70 V ±20 ±40 ±20 ±40 µV TMIN < TA < TMAX ±125 ±150 µV Voltage Offset Drift2 TMIN < TA < TMAX ±0.1 ±0.5 ±0.1 ±0.8 µV/°C Input Bias Current (IB) ±0.35 ±0.7 ±0.35 ±0.7 nA TMIN < TA < TMAX ±10 ±25 nA VCM = 70 V, Over-The-Top 3.5 8 12 3.5 8 12 µA TMIN < TA < TMAX 1.75 14.8 1.5 15 µA 0 V < VCM < 70 V, VSY = 0 V 0.001 1 0.001 1 µA TMIN < TA < TMAX 10 10 µA Input Offset Current (IOS) ±0.35 ±0.7 ±0.35 ±0.7 nA TMIN < TA < TMAX ±5 ±15 nA VCM = 70 V, Over-The-Top3 ±0.05 ±0.065 ±0.05 ±0.065 µA TMIN < TA < TMAX ±0.09 ±0.1 µA Common-Mode Rejection VCM = −0.1 V to +70 V 123 140 123 140 dB Ratio (CMRR) TMIN < TA < TMAX 114 114 dB VCM = 0.25 V to 3.5 V 116 134 116 134 dB TMIN < TA < TMAX 110 110 dB Common-Mode Input Range Guaranteed by CMRR tests −0.1 +70 −0.1 +70 V Large Signal Voltage Gain (AOL) ΔVOUT = 4 V 126 150 126 150 dB TMIN < TA < TMAX 120 120 dB ΔVOUT = 4 V, RL = 10 kΩ 112 122 112 122 dB TMIN < TA < TMAX 106 106 dB NOISE PERFORMANCE Input Voltage Noise Frequency (f) = 0.1 Hz to 10 Hz 400 400 nV p-p 1/f noise corner 6 6 Hz f = 100 Hz 18 18 nV/√Hz Over-The-Top f = 100 Hz, VCM > 5 V 20 20 nV/√Hz Input Current Noise f = 100 Hz 0.15 0.15 pA/√Hz Over-The-Top f = 100 Hz, VCM > 5 V 1.8 1.8 pA/√Hz DYNAMIC PERFORMANCE Slew Rate ΔVOUT = 2 V 0.15 0.4 0.15 0.4 V/μs TMIN < TA < TMAX 0.1 0.1 V/μs Gain Bandwidth Product (GBP) Test frequency (fTEST) = 25 kHz 1 1.05 1 1.05 MHz TMIN < TA < TMAX 0.95 0.95 MHz Phase Margin 55 55 Degrees 1% Settling Time ΔVOUT = ±2 V TBD TBD μs 0.1% Settling Time ΔVOUT = ±2 V TBD TBD μs Total Harmonic Distortion Plus f = 10 kHz, VOUT = 2 V p-p, RL = 0.15 0.4 0.15 0.4 % Noise (THD + N) 10 kΩ, bandwidth = 80 kHz Rev. PrA | Page 3 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS SPECIFICATIONS 5 V SUPPLY ±15 V SUPPLY ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT PROTECTION OVER-THE-TOP OPERATION CONSIDERATIONS OUTPUT SHUTDOWN PIN (SHDN) APPLICATIONS INFORMATION LARGE RESISTOR GAIN OPERATION RECOMMENDED VALUES FOR VARIOUS GAINS NOISE DISTORTION POWER DISSIPATION AND THERMAL SHUTDOWN CIRCUIT LAYOUT CONSIDERATIONS POWER SUPPLY BYPASSING GROUNDING ESD PROTECTION WHEN POWERED RELATED PRODUCTS TYPICAL APPLICATIONS OUTLINE DIMENSIONS