Datasheet STM32WB5MMG (STMicroelectronics) - 12
| Fabricante | STMicroelectronics |
| Descripción | Bluetooth Low Energy 5.0 and 802.15.4 module |
| Páginas / Página | 31 / 12 — STM32WB5MMG. Layout recommendations. 5.2.3. Ground plane. Figure 6. … |
| Formato / tamaño de archivo | PDF / 3.7 Mb |
| Idioma del documento | Inglés |
STM32WB5MMG. Layout recommendations. 5.2.3. Ground plane. Figure 6. STM32WB5MMG ground plane layout. 5.2.4. Sensitive GPIOs
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 12 link to page 13 link to page 14
STM32WB5MMG Layout recommendations 5.2.3 Ground plane
Here are some recommendations with respect to the ground plane design: • Do not route any tracks to the right of the STM32WB5MMG and keep a large ground plane with the associated ground via. • Route the tracks down directly on the top layer or with via to the other layers. • The ground plane must include the presence of vias (distance between two vias = 2 mm).
Figure 6. STM32WB5MMG ground plane layout
Tracks Ground via Ground plane
5.2.4 Sensitive GPIOs
This board contains three sensitive GPIOs as defined below: • PB10 • PB11 • PC5 The GPIO locations are illustrated in Figure 7 It is recommendedl to add a 3.3 pF capacitor in a small package (0201 or smaller) as close as possible to PB10, PB11 and PC5 outputs of the STM32WB5MMG and also to border the GPIO tracks with ground.
Figure 7. Sensitive GPIO location
Superposition of Layer 1 Layer 4 four layers Sensitive GPIO location on layer 1 Sensitive GPIO location on layer 4
5.2.5 Four layer reference board design
The reference schematics are illustrated in Figure 8 and the associated PCB layout is illustrated in Figure 9 By using the first external pad ring, the mother board on which the module is soldered may be designed with only two layers. Using all the pads, the mother board must be designed with 4 layers.
DS13252
-
Rev 1 page 12/31
Document Outline 1 Introduction 2 Description 3 Available peripherals 4 Pin description 5 Recommendations 5.1 Pin recommendations 5.2 Layout recommendations 5.2.1 STM32WB5MMG placement 5.2.2 Enclosure effects 5.2.3 Ground plane 5.2.4 Sensitive GPIOs 5.2.5 Four layer reference board design 6 Electrical characteristics 6.1 Operating conditions 6.2 Power consumption 6.3 RF characteristics 6.4 Antenna radiation patterns and efficiency 7 Thermal characteristics 8 Solder re-flow recommendation 9 Package information 9.1 SiP-LGA86 package information 9.1.1 Device marking for SiP-LGA86 10 Ordering information 11 Tape and reel packing 12 Certification 12.1 CE certification 12.2 FCC certification 12.3 ISED certification 12.4 JRF certification 12.5 NCC certification 12.6 SRRC certification Revision history Contents List of tables List of figures
STM32WB5MMG Layout recommendations 5.2.3 Ground plane
Here are some recommendations with respect to the ground plane design: • Do not route any tracks to the right of the STM32WB5MMG and keep a large ground plane with the associated ground via. • Route the tracks down directly on the top layer or with via to the other layers. • The ground plane must include the presence of vias (distance between two vias = 2 mm).
Figure 6. STM32WB5MMG ground plane layout
Tracks Ground via Ground plane
5.2.4 Sensitive GPIOs
This board contains three sensitive GPIOs as defined below: • PB10 • PB11 • PC5 The GPIO locations are illustrated in Figure 7 It is recommendedl to add a 3.3 pF capacitor in a small package (0201 or smaller) as close as possible to PB10, PB11 and PC5 outputs of the STM32WB5MMG and also to border the GPIO tracks with ground.
Figure 7. Sensitive GPIO location
Superposition of Layer 1 Layer 4 four layers Sensitive GPIO location on layer 1 Sensitive GPIO location on layer 4
5.2.5 Four layer reference board design
The reference schematics are illustrated in Figure 8 and the associated PCB layout is illustrated in Figure 9 By using the first external pad ring, the mother board on which the module is soldered may be designed with only two layers. Using all the pads, the mother board must be designed with 4 layers.
DS13252
-
Rev 1 page 12/31
Document Outline 1 Introduction 2 Description 3 Available peripherals 4 Pin description 5 Recommendations 5.1 Pin recommendations 5.2 Layout recommendations 5.2.1 STM32WB5MMG placement 5.2.2 Enclosure effects 5.2.3 Ground plane 5.2.4 Sensitive GPIOs 5.2.5 Four layer reference board design 6 Electrical characteristics 6.1 Operating conditions 6.2 Power consumption 6.3 RF characteristics 6.4 Antenna radiation patterns and efficiency 7 Thermal characteristics 8 Solder re-flow recommendation 9 Package information 9.1 SiP-LGA86 package information 9.1.1 Device marking for SiP-LGA86 10 Ordering information 11 Tape and reel packing 12 Certification 12.1 CE certification 12.2 FCC certification 12.3 ISED certification 12.4 JRF certification 12.5 NCC certification 12.6 SRRC certification Revision history Contents List of tables List of figures