Datasheet ADSP-21065L-EP (Analog Devices) - 7

Enhanced Product ADSP-21065L-EP Table 2. Pin Descriptions (Continued) Pin Type Function
CLKIN I
Clock In.
Used in conjunction with XTAL, configures the ADSP-21065L-EP to use either its internal clock generator or an external clock source. The external crystal should be rated at 1 frequency. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. The ADSP-21065L-EP’s internal clock generator multiplies the 1 clock to generate 2 clock for its core and SDRAM. It drives 2 clock out on the SDCLKx pins for the SDRAM interface to use. See also SDCLKx. Connecting the 1 external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21065L-EP to use the external clock source. The instruction cycle rate is equal to 2 CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency. RESET I/A
Processor Reset.
Resets the ADSP-21065L-EP to a known state and begins execution at the program memory location specified by the hardware reset vector address. This input must be asserted at power-up. TCK I
Test Clock (JTAG).
Provides an asynchronous clock for JTAG boundary scan. TMS I/S
Test Mode Select (JTAG).
Used to control the test state machine. TMS has a 20 k internal pull-up resistor. TDI I/S
Test Data Input (JTAG).
Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up resistor. TDO O
Test Data Output (JTAG).
Serial scan output of the boundary scan path. TRST I/A
Test Reset (JTAG).
Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21065L-EP. TRST has a 20 k internal pull-up resistor. EMU (O/D) O
Emulation Status.
Must be connected to the ADSP-21065L-EP EZ-ICE target board connector only. BMSTR O
Bus Master Output.
In a multiprocessor system, indicates whether the ADSP-21065L-EP is current bus master of the shared external bus. The ADSP-21065L-EP drives BMSTR high only while it is the bus master. In a single-processor system (ID = 00), the processor drives this pin high. CAS I/O/T
SDRAM Column Access Strobe.
Provides the column address. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. RAS I/O/T
SDRAM Row Access Strobe.
Provides the row address. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. SDWE I/O/T
SDRAM Write Enable.
In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. DQM O/T
SDRAM Data Mask.
In write mode, DQM has a latency of zero and is used to block write operations. SDCLK1-0 I/O/S/T
SDRAM 2

Clock Output.
In systems with multiple SDRAM devices connected in parallel, supports the corresponding increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. SDCKE I/O/T
SDRAM Clock Enable.
Enables and disables the CLK signal. For details, see the data sheet supplied with your SDRAM device. SDA10 O/T
SDRAM A10 Pin.
Enables applications to refresh an SDRAM in parallel with a host access. XTAL O
Crystal Oscillator Terminal.
Used in conjunction with CLKIN to enable the ADSP-21065L-EP’s internal clock generator or to disable it to use an external clock source. See CLKIN. PWM_EVENT1-0 I/O/A
PWM Output/Event Capture.
In PWMOUT mode, is an output pin and functions as a timer counter. In WIDTH_CNT mode, is an input pin and functions as a pulse counter/event capture. VDD P
Power Supply.
Nominally +3.3 V dc. (33 pins) GND G
Power Supply Return.
(37 pins) NC
Do Not Connect.
Reserved pins which must be left open and unconnected. (7 pins) A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, T = Three-State (when SBTS is asserted, or when the ADSP-21065L-EP is a bus slave) Rev. B | Page 7 of 14 | September 2017 Document Outline Summary Enhanced Product (EP) Features Features Table of Contents Revision History General Description Pin Function Descriptions Specifications Operating Conditions Absolute Maximum Ratings ESD Caution Package Marking Information Environmental Conditions Thermal Characteristics 208-LEAD MQFP Pin Configuration Outline Dimensions Ordering Guide