Datasheet ADSP-21369 (Analog Devices) - 7

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ADSP-21369 FAMILY PERIPHERAL ARCHITECTURE Table 4. External Memory for SDRAM Addresses
The processor contains a rich set of peripherals that support a
Size in
wide variety of applications including high quality audio, medi-
Bank Words Address Range
cal imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other Bank 0 62M 0x0020 0000–0x03FF FFFF applications. Bank 1 64M 0x0400 0000–0x07FF FFFF
External Port
Bank 2 64M 0x0800 0000–0x0BFF FFFF The external port interface supports access to the external mem- Bank 3 64M 0x0C00 0000–0x0FFF FFFF ory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be pro- grammed as either asynchronous or synchronous memory. The devices and DIMMs (dual inline memory module), while the external ports of the processor are comprised of the following second is an asynchronous memory controller intended to modules. interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting • An Asynchronous Memory Interface which communicates any desired combination of synchronous and asynchronous with SRAM, FLASH, and other devices that meet the stan- device types. Non-SDRAM external memory address space is dard asynchronous SRAM access protocol. The AMI shown in Table 5. supports 14M words of external memory in bank 0 and 16M words of external memory in bank 1, bank 2, and
Table 5. External Memory for Non-SDRAM Addresses
bank 3. • An SDRAM controller that supports a glueless interface
Size in
with any of the standard SDRAMs. The SDC supports 62M
Bank Words Address Range
words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. Bank 0 14M 0x0020 0000–0x00FF FFFF • Arbitration Logic to coordinate core and DMA transfers Bank 1 16M 0x0400 0000–0x04FF FFFF between internal and external memory over the external Bank 2 16M 0x0800 0000–0x08FF FFFF port. Bank 3 16M 0x0C00 0000–0x0CFF FFFF • A Shared Memory Interface that allows the connection of up to four processors to create shared external bus systems.
Shared External Memory SDRAM Controller
The ADSP-21369 processor supports connecting to common The SDRAM controller provides an interface of up to four sepa- shared external memory with other ADSP-21369 processors to rate banks of industry-standard SDRAM devices or DIMMs, at create shared external bus processor systems. This support speeds up to f . Fully compliant with the SDRAM standard, SCLK includes: each bank has its own memory select line (MS0–MS3), and can • Distributed, on-chip arbitration for the shared external bus be configured to contain between 16M bytes and 128M bytes of memory. SDRAM external memory address space is shown in • Fixed and rotating priority bus arbitration Table 4. • Bus time-out logic A set of programmable timing parameters is available to config- • Bus lock ure the SDRAM banks to support slower memory devices. The Multiple processors can share the external bus with no addi- memory banks can be configured as either 32 bits wide for max- tional arbitration logic. Arbitration logic is included on-chip to imum performance and bandwidth or 16 bits wide for allow the connection of up to four processors. minimum device count and lower system cost. Bus arbitration is accomplished through the BR1–4 signals and The SDRAM controller address, data, clock, and control pins the priority scheme for bus arbitration is determined by the set- can drive loads up to distributed 30 pF loads. For larger memory ting of the RPBA pin. Table 8 provides descriptions of the pins systems, the SDRAM controller external buffer timing should used in multiprocessor systems. be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF.
External Port Throughput External Memory
The throughput for the external port, based on 166 MHz clock and 32-bit data bus, is 221M bytes/s for the AMI and 664M The external port provides a high performance, glueless inter- bytes/s for SDRAM. face to a wide variety of industry-standard memory devices. The 32-bit wide bus can be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM Rev. H | Page 7 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide