Datasheet ADSP-21369 (Analog Devices) - 10

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ADSP-21369 Peripheral Timers Delay Line DMA
Three general-purpose timers can generate periodic interrupts The processor provides delay line DMA functionality. This and be independently set to operate in one of three modes: allows processor reads and writes to external delay line buffers • Pulse waveform generation mode (in external memory, SRAM, or SDRAM) with limited core interaction. • Pulse width count/capture mode • External event watchdog mode
SYSTEM DESIGN
Each general-purpose timer has one bidirectional pin and four The following sections provide an introduction to system design registers that implement its mode of operation: a 6-bit configu- options and power supply issues. ration register, a 32-bit count register, a 32-bit period register,
Program Booting
and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers The internal memory of the processors can be booted up at sys- independently. tem power-up from an 8-bit EPROM via the external port, an SPI master or slave, or an internal boot. Booting is determined
2-Wire Interface Port (TWI)
by the boot configuration (BOOT_CFG1–0) pins (see Table 7 The TWI is a bidirectional 2-wire serial bus used to move 8-bit and the processor hardware reference). Selection of the boot data while maintaining compliance with the I2C bus protocol. source is controlled via the SPI as either a master or slave device, The TWI master incorporates the following features: or it can immediately begin executing from ROM. • Simultaneous master and slave operation on multiple
Table 7. Boot Mode Selection
device systems with support for multimaster data arbitration
BOOT_CFG1–0 Booting Mode
• Digital filtering and timed event processing 00 SPI Slave Boot • 7-bit and 10-bit addressing 01 SPI Master Boot • 100 kbps and 400 kbps data rates 10 EPROM/FLASH Boot 11 No boot (processor executes from • Low interrupt rate internal ROM after reset)
I/O PROCESSOR FEATURES Power Supplies
The I/O processor provides many channels of DMA, and con- trols the extensive set of peripherals described in the previous The processors have separate power supply connections for the sections. internal (V ), external (V ), and analog (A /A ) power DDINT DDEXT VDD VSS supplies. The internal and analog supplies must meet the 1.3 V
DMA Controller
requirement for the 400 MHz device and 1.2 V for the The processor’s on-chip DMA controller allows data transfers 333 MHz and 266 MHz devices. The external supply must meet without processor intervention. The DMA controller operates the 3.3 V requirement. All external supply pins must be con- independently and invisibly to the processor core, allowing nected to the same power supply. DMA operations to occur while the core is simultaneously exe- Note that the analog supply pin (A ) powers the processor’s VDD cuting its program instructions. DMA transfers can occur internal clock generator PLL. To produce a stable clock, it is rec- between the processor’s internal memory and its serial ports, the ommended that PCB designs use an external filter circuit for the SPI-compatible (serial peripheral interface) ports, the IDP A pin. Place the filter components as close as possible to the VDD (input data port), the parallel data acquisition port (PDAP), or A /A pins. For an example circuit, see Figure 3. (A recom- VDD VSS the UART. mended ferrite chip is the muRata BLM18AG102SN1D). To Thirty four channels of DMA are available on the ADSP-2136x reduce noise coupling, the PCB should use a parallel pair of processors as shown in Table 6. power and ground planes for V and GND. Use wide traces DDINT to connect the bypass capacitors to the analog power (A ) and VDD
Table 6. DMA Channels
ground (A ) pins. Note that the A and A pins specified in VSS VDD VSS Figure 3 are inputs to the processor and not the analog ground
Peripheral DMA Channels
plane on the board—the A pin should connect directly to dig- VSS SPORTs 16 ital ground (GND) at the chip. PDAP 8 SPI 2 UART 4 External Port 2 Memory-to-Memory 2 Rev. H | Page 10 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide