Datasheet ADP1752, ADP1753 (Analog Devices) - 5

Data Sheet ADP1752/ADP1753 ABSOLUTE MAXIMUM RATINGS Table 3.
Junction-to-ambient thermal resistance (θJA) of the package is
Parameter Rating
based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on VIN to GND −0.3 V to +4.0 V the application and board layout. In applications where high VOUT to GND −0.3 V to VIN maximum power dissipation exists, close attention to thermal EN to GND −0.3 V to VIN board design is required. The value of θ SS to GND −0.3 V to V JA may vary, depending IN on PCB material, layout, and environmental conditions. The PG to GND −0.3 V to +4.0 V specified values of θ SENSE/ADJ to GND −0.3 V to V JA are based on a 4-layer, 4 in × 3 in circuit IN board. Refer to JEDEC JESD51-7 for detailed information about Storage Temperature Range −65°C to +150°C board construction. For more information, see the AN-772 Junction Temperature Range −40°C to +125°C Application Note, A Design and Manufacturing Guide for the Junction Temperature 150°C Lead Frame Chip Scale Package (LFCSP) at www.analog.com. Soldering Conditions JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum ΨJB is the junction-to-board thermal characterization parameter with units of °C/W. Ψ Ratings may cause permanent damage to the product. This is a JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12 document, stress rating only; functional operation of the product at these Guidelines for Reporting and Using Electronic Package Thermal or any other conditions above those indicated in the operational Information, states that thermal characterization parameters are section of this specification is not implied. Operation beyond not the same as thermal resistances. Ψ the maximum operating conditions for extended periods may JB measures the component affect product reliability. power flowing through multiple thermal paths rather than through a single path as in thermal resistance, θJB. Therefore,
THERMAL DATA
ΨJB thermal paths include convection from the top of the package Absolute maximum ratings apply individually only, not in as well as radiation from the package, factors that make ΨJB more combination. The ADP1752/ADP1753 may be damaged if the useful in real-world applications. Maximum junction temperature junction temperature limits are exceeded. Monitoring ambient (TJ) is calculated from the board temperature (TB) and the power temperature does not guarantee that T dissipation (P J is within the specified D) using the following formula: temperature limits. In applications with high power dissipation TJ = TB + (PD × ΨJB) and poor thermal resistance, the maximum ambient tempera- Refer to the JEDEC JESD51-8 and JESD51-12 documents for more ture may need to be derated. In applications with moderate detailed information about Ψ power dissipation and low PCB thermal resistance, the maximum JB. ambient temperature can exceed the maximum limit as long as
THERMAL RESISTANCE
the junction temperature is within specification limits. The θJA and ΨJB are specified for the worst-case conditions, that is, a junction temperature (TJ) of the device is dependent on the device soldered in a circuit board for surface-mount packages. ambient temperature (TA), the power dissipation of the device (P
Table 4. Thermal Resistance
D), and the junction-to-ambient thermal resistance of the package (θJA). TJ is calculated using the following formula:
Package Type θJA ΨJB Unit
T 16-Lead LFCSP with Exposed Pad (CP-16-23) 42 25.5 °C/W J = TA + (PD × θJA).
ESD CAUTION
Rev. H | Page 5 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START FUNCTION (ADP1752/ADP1753) ADJUSTABLE OUTPUT VOLTAGE (ADP1753) ENABLE FEATURE POWER-GOOD FEATURE REVERSE CURRENT PROTECTION FEATURE APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE