Datasheet ADP1752, ADP1753 (Analog Devices) - 6

ADP1752/ADP1753 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS UT UT N N UT UT N N VI VI VO VO VI VI VO VO 16 15 14 13 16 15 14 13 VIN 1 12 VOUT VIN 1 12 VOUT VIN 2 ADP1752 11 VOUT VIN 2 ADP1753 11 VOUT VIN 3 TOP VIEW 10 VOUT TOP VIEW (Not to Scale) VIN 3 10 VOUT (Not to Scale) EN 4 9 SENSE EN 4 9 ADJ 5 6 7 8 5 6 7 8 PG ND SS NC PG ND SS NC G G NOTES NOTES 1. NC = NO CONNECT. 1. NC = NO CONNECT. 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
003
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
004
BE CONNECTED TO THE GROUND PLANE ON THE BOARD. BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07718- 07718- Figure 3. ADP1752 Pin Configuration Figure 4. ADP1753 Pin Configuration
Table 5. Pin Function Descriptions ADP1752 ADP1753 Pin No. Pin No. Mnemonic Description
1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all five VIN pins must be connected to the source. 4 4 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to VIN. 5 5 PG Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal output voltage, PG immediately transitions low. 6 6 GND Ground. 7 7 SS Soft Start. A capacitor connected to this pin determines the soft start time. 8 8 NC Not Connected. No internal connection. 9 N/A SENSE Sense. This pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. N/A 9 ADJ Adjust. A resistor divider from VOUT to ADJ sets the output voltage. 10, 11, 12, 10, 11, 12, VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that 13, 14 13, 14 all five VOUT pins must be connected to the load. 17 (EPAD) 17 (EPAD) Exposed The exposed pad on the bottom of the LFCSP package enhances thermal performance and paddle is electrically connected to GND inside the package. It is recommended that the exposed (EPAD) pad be connected to the ground plane on the board. Rev. H | Page 6 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START FUNCTION (ADP1752/ADP1753) ADJUSTABLE OUTPUT VOLTAGE (ADP1753) ENABLE FEATURE POWER-GOOD FEATURE REVERSE CURRENT PROTECTION FEATURE APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE