Datasheet ADP5030 (Analog Devices) - 5

ADP5030 ABSOLUTE MAXIMUM RATINGS Table 3.
maximum power dissipation exists, close attention to thermal board design is required.
Parameter Rating
VIN1, EN1, MSEL to GND −0.3 V to +6.5 V The value of θJA may vary, depending on PCB material, layout, VOUT1, VOUT2 to GND −0.3 V to V and environmental conditions. The specified values of θ IN1 JA are VIN2, VIN3, EN2, GPIN1, GPIN2, GPIN3 to GND −0.3 V to +3.6 V based on a 4-layer, 4-inch × 3-inch circuit board. Refer to JEDEC VOUT3, GPOUT1 to GND −0.3 V to V JESD51-9 for detailed information about board construction. IN2 GPOUT2, GPOUT3 to GND −0.3 V to V For more information, see the AN-617 Application Note, IN3 Storage Temperature Range −65°C to +150°C MicroCSPTM Wafer Level Chip Scale Package at www.analog.com. Operating Junction Temperature Range −40°C to +125°C ΨJB is the junction-to-board thermal characterization parameter Soldering Conditions JEDEC J-STD-020 with units of °C/W. The ΨJB of the package is based on modeling Stresses above those listed under Absolute Maximum Ratings and calculation using a 4-layer board. The JEDEC JESD51-12 may cause permanent damage to the device. This is a stress document, Guidelines for Reporting and Using Electronic Package rating only; functional operation of the device at these or any Thermal Information, states that thermal characterization param- other conditions above those indicated in the operational eters are not the same as thermal resistances. ΨJB measures the section of this specification is not implied. Exposure to absolute component power flowing through multiple thermal paths rather maximum rating conditions for extended periods may affect than through a single path, as in thermal resistance (θJB). There- device reliability. fore, ΨJB thermal paths include convection from the top of the package, as well as radiation from the package, factors that make
THERMAL DATA
ΨJB more useful in real-world applications. Maximum junction Absolute maximum ratings apply individually only, not in temperature (TJ) is calculated from the board temperature (TB) combination. The ADP5030 can be damaged when the junction and the power dissipation (PD) using the following formula: temperature limits are exceeded. Monitoring ambient tempera- TJ = TB + (PD × ΨJB) ture does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with Refer to the JEDEC JESD51-8 and JESD51-12 documents for high power dissipation and poor PCB thermal resistance, the more detailed information about ΨJB. maximum ambient temperature may need to be derated. In
THERMAL RESISTANCE
applications with moderate power dissipation and low PCB θJA and ΨJB are specified for the worst-case conditions, that is, a thermal resistance, the maximum ambient temperature can device soldered in a circuit board for surface-mount packages. exceed the maximum limit as long as the junction temperature is within specification limits.
Table 4. Thermal Resistance
The junction temperature (T
Package Type θ
J) of the device is dependent on the
JA ΨJB Unit
ambient temperature (TA), the power dissipation of the device 16-Ball, 0.4 mm Pitch WLCSP 66.6 18.5 °C/W (PD), and the junction-to-ambient thermal resistance of the package (θJA). Maximum junction temperature (TJ) is calculated from the ambient temperature (T
ESD CAUTION
A) and power dissipation (PD) using the following formula: TJ = TA + (PD × θJA) The junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high Rev. B | Page 5 of 5 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION LDO2 AND LOAD SWITCH ACTIVATION LOGIC SEQUENCING CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE