Datasheet AD8561 (Analog Devices) - 8

AD8561 INPUT STAGE AND BIAS CURRENTS
The input signal is connected directly to the noninverting input The AD8561 uses a PNP differential input stage that enables of the comparator. The output is fed back to the inverting input the input common-mode range to extend all the way from the through R1 and R2. The ratio of R1 to R1 + R2 establishes the negative supply rail to within 2.2 V of the positive supply rail. width of the hysteresis window with VREF setting the center of The input common-mode voltage can be found as the average the window, or the average switching voltage. The Q output will of the voltage at the two inputs of the device. To ensure the switch high when the input voltage is greater than VHI and will fastest response time, care should be taken not to allow the not switch low again until the input voltage is less than VLO as input common-mode voltage to exceed either of these voltages. given in Equation 1: The input bias current for the AD8561 is 3 μA. As with any PNP differential input stage, this bias current will go to zero on V = ( ) R1 + HI V + –1–V REF V REF an input that is high and will double on an input that is low. R1+ R2 Care should be taken in choosing resistor values to be con- (1) nected to the inputs as large resistors could cause significant ⎛ R1 ⎞ V =V voltage drops due to the input bias current. LO REF 1– R1 ⎝⎜ + R2⎠⎟ The input capacitance for the AD8561 is typically 3 pF. This is measured by inserting a 5 kΩ source resistance to the input and Where V+ is the positive supply voltage. measuring the change in propagation delay. The capacitor CF can also be added to introduce a pole into the feedback network. This has the effect of increasing the amount
USING HYSTERESIS
of hysteresis at high frequencies. This can be useful when com- Hysteresis can easily be added to a comparator through the paring a relatively slow signal in a high frequency noise environ- addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desir- 1 ment. At frequencies greater than f , the hysteresis able for the output to toggle between states when the input P = 2π CFR2 signal is near the switching threshold. Figure 17 shows a window approaches VHI = V+ – 1 V and VLO = 0 V. At frequen- method for configuring the AD8561 with hysteresis. cies less than fP the threshold voltages remain as in Equation 1.
COMPARATOR SIGNAL R1 R2 VREF CF
Figure 17. Configuring the AD8561 with Hysteresis –8– Rev. D Document Outline Features Applications General Description Pin Configurations Specifications Electrical Specifications Absolute Maximum Ratings Typical Performance Characteristics Applications Optimizing High Speed Performance Replacing the LT1016 Increasing Output Swing Output Loading Considerations Setup and Hold Times for Latching the Output Input Stage and Bias Currents Using Hysteresis SPICE Model Outline Dimensions Ordering Guide Revision History