Datasheet ADCMP600, ADCMP601, ADCMP602 (Analog Devices) - 5

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ADCMP600/ADCMP601/ADCMP602 TIMING INFORMATION
Figure 2 il ustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V LATCH ENABLE tS tPL tH DIFFERENTIAL VIN VN ± VOS INPUT VOLTAGE VOD tPDL tPLOH Q OUTPUT 50%
025
tF
05914- Figure 2. System Timing Diagram
Table 2. Timing Descriptions Symbol Timing Description
t Input to output high delay Propagation delay measured from the time the input signal crosses the reference (± the PDH input offset voltage) to the 50% point of an output low-to-high transition. t Input to output low delay Propagation delay measured from the time the input signal crosses the reference (± the PDL input offset voltage) to the 50% point of an output high-to-low transition. t Latch enable to output high delay Propagation delay measured from the 50% point of the latch enable signal low-to-high PLOH transition to the 50% point of an output low-to-high transition. t Latch enable to output low delay Propagation delay measured from the 50% point of the latch enable signal low-to-high PLOL transition to the 50% point of an output high-to-low transition. t Minimum hold time Minimum time after the negative transition of the latch enable signal that the input signal H must remain unchanged to be acquired and held at the outputs. t Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change. PL t Minimum setup time Minimum time before the negative transition of the latch enable signal occurs that an S input signal change must be present to be acquired and held at the outputs. t Output rise time Amount of time required to transition from a low to a high output as measured at the 20% R and 80% points. t Output fall time Amount of time required to transition from a high to a low output as measured at the 20% F and 80% points. V Voltage overdrive Difference between the input voltages V and V . OD A B Rev. A | Page 5 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Timing Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Information Power/Ground Layout and Bypassing TTL-/CMOS-Compatible Output Stage Using/Disabling the Latch Feature Optimizing Performance Comparator Propagation Delay Dispersion Comparator Hysteresis Crossover Bias Point Minimum Input Slew Rate Requirement Typical Application Circuits Outline Dimensions Ordering Guide