Datasheet ADCMP600, ADCMP601, ADCMP602 (Analog Devices) - 13
| Fabricante | Analog Devices |
| Descripción | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators |
| Páginas / Página | 16 / 13 — ADCMP600/ADCMP601/ADCMP602. TYPICAL APPLICATION CIRCUITS. 0.1µF. 2.5V. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 291 Kb |
| Idioma del documento | Inglés |
ADCMP600/ADCMP601/ADCMP602. TYPICAL APPLICATION CIRCUITS. 0.1µF. 2.5V. 2kΩ. ADCMP600. OUTPUT. CMOS. PWM OUTPUT. INPUT. 1.25V. ±50mV. 10kΩ. REF
Línea de modelo para esta hoja de datos
Versión de texto del documento
ADCMP600/ADCMP601/ADCMP602 TYPICAL APPLICATION CIRCUITS 5V 0.1µF 2.5V 2kΩ 2kΩ ADCMP600 OUTPUT 0.1µF
019 05914-
CMOS
Figure 22. Self-Biased, 50% Slicer
ADCMP600 PWM OUTPUT INPUT 1.25V ±50mV INPUT 1.25V 10kΩ REF CMOS 10kΩ VDD 2.5V TO 5V ADCMP601 100Ω ADCMP600 CMOS LE/HYS 10kΩ 82pF 40kΩ
020 022 05914- 05914- Figure 23. LVDS-to-CMOS Receiver Figure 25. Oscillator and Pulse-Width Modulator
2.5V TO 5V 2.5V 10kΩ ADCMP601 20kΩ OUTPUT ADCMP601 1.5MHz TO 30MHz LE/HYS DIGITAL 74 AHC INPUT LE/HYS 1G07 20kΩ 82pF CONTROL VOLTAGE
021
HYSTERESIS
023
0V TO 2.5V 100kΩ 100kΩ CURRENT 10kΩ
05914- 05914- Figure 24. Voltage-Controlled Oscillator Figure 26. Hysteresis Adjustment with Latch Rev. A | Page 13 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Timing Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Information Power/Ground Layout and Bypassing TTL-/CMOS-Compatible Output Stage Using/Disabling the Latch Feature Optimizing Performance Comparator Propagation Delay Dispersion Comparator Hysteresis Crossover Bias Point Minimum Input Slew Rate Requirement Typical Application Circuits Outline Dimensions Ordering Guide
019 05914-
CMOS
Figure 22. Self-Biased, 50% Slicer
ADCMP600 PWM OUTPUT INPUT 1.25V ±50mV INPUT 1.25V 10kΩ REF CMOS 10kΩ VDD 2.5V TO 5V ADCMP601 100Ω ADCMP600 CMOS LE/HYS 10kΩ 82pF 40kΩ
020 022 05914- 05914- Figure 23. LVDS-to-CMOS Receiver Figure 25. Oscillator and Pulse-Width Modulator
2.5V TO 5V 2.5V 10kΩ ADCMP601 20kΩ OUTPUT ADCMP601 1.5MHz TO 30MHz LE/HYS DIGITAL 74 AHC INPUT LE/HYS 1G07 20kΩ 82pF CONTROL VOLTAGE
021
HYSTERESIS
023
0V TO 2.5V 100kΩ 100kΩ CURRENT 10kΩ
05914- 05914- Figure 24. Voltage-Controlled Oscillator Figure 26. Hysteresis Adjustment with Latch Rev. A | Page 13 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Timing Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Information Power/Ground Layout and Bypassing TTL-/CMOS-Compatible Output Stage Using/Disabling the Latch Feature Optimizing Performance Comparator Propagation Delay Dispersion Comparator Hysteresis Crossover Bias Point Minimum Input Slew Rate Requirement Typical Application Circuits Outline Dimensions Ordering Guide