Datasheet AD9364 (Analog Devices) - 4

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AD9364 Data Sheet Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTER, 800 MHz Output S22 −10 dB Maximum Output Power 8 dBm 1 MHz tone into 50 Ω load Modulation Accuracy (EVM) −40 dB 19.2 MHz reference clock Third-Order Output Intermod- OIP3 23 dBm ulation Intercept Point Carrier Leakage −50 dBc 0 dB attenuation −32 dBc 40 dB attenuation Noise Floor −157 dBm/Hz 90 MHz offset TRANSMITTER, 2.4 GHz Output S22 −10 dB Maximum Output Power 7.5 dBm 1 MHz tone into 50 Ω load Modulation Accuracy (EVM) −40 dB 40 MHz reference clock Third-Order Output Intermod- OIP3 19 dBm ulation Intercept Point Carrier Leakage −50 dBc 0 dB attenuation −32 dBc 40 dB attenuation Noise Floor −156 dBm/Hz 90 MHz offset TRANSMITTER, 5.5 GHz Output S22 −10 dB Maximum Output Power 6.5 dBm 7 MHz tone into 50 Ω load Modulation Accuracy (EVM) −36 dB 40 MHz reference clock (doubled internally for RF synthesizer) Third-Order Output Intermod- OIP3 17 dBm ulation Intercept Point Carrier Leakage −50 dBc 0 dB attenuation −30 dBc 40 dB attenuation Noise Floor −151.5 dBm/Hz 90 MHz offset TX MONITOR INPUT (TX_MON) Maximum Input Level 4 dBm Dynamic Range 66 dB Accuracy 1 dB LO SYNTHESIZER LO Frequency Step 2.4 Hz 2.4 GHz, 40 MHz reference clock Integrated Phase Noise 800 MHz 0.13 ° rms 100 Hz to 100 MHz, 30.72 MHz reference clock (doubled internal y for RF synthesizer) 2.4 GHz 0.37 ° rms 100 Hz to 100 MHz, 40 MHz reference clock 5.5 GHz 0.59 ° rms 100 Hz to 100 MHz, 40 MHz reference clock (doubled internal y for RF synthesizer) REFERENCE CLOCK (REF_CLK) REF_CLK is either the input to the XTALP/XTALN pins or a line directly to the XTALN pin Input Frequency Range 19 50 MHz Crystal input 10 80 MHz External oscillator Signal Level 1.3 V p-p AC-coupled external oscillator AUXILIARY CONVERTERS ADC Resolution 12 Bits Input Voltage Minimum 0.05 V Maximum VDDA1P3_BB − 0.05 V DAC Resolution 10 Bits Rev. C | Page 4 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide