Datasheet AD9364 (Analog Devices) - 10

AD9364 Data Sheet ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE Table 11.
The AD9364 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow
Parameter Rating
temperature is 260°C. VDDx to VSSx −0.3 V to +1.4 V VDD_INTERFACE to VSSx −0.3 V to +3.0 V
THERMAL RESISTANCE
VDD_GPO to VSSx −0.3 V to +3.9 V θJA is specified for the worst-case conditions, that is, a device Logic Inputs and Outputs to −0.3 V to VDD_INTERFACE + 0.3 V soldered in a circuit board for surface-mount packages. VSSx Input Current to Any Pin ±10 mA
Table 12. Thermal Resistance
Except Supplies
Airflow
RF Inputs (Peak Power) 2.5 dBm
Package Velocity
Tx Monitor Input Power (Peak 9 dBm
Type (m/sec) θ 1, 2 1, 3 1, 4 1, 2 JA θJC θJB

JT Unit
Power) 144-Ball 0 32.3 9.6 20.2 0.27 °C/W Package Power Dissipation (T CSP_BGA JMAX − TA)/θJA 1.0 29.6 0.43 °C/W Maximum Junction 110°C 2.5 27.8 0.57 °C/W Temperature (TJMAX) 1 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board. Operating Temperature Range −40°C to +85°C 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Storage Temperature Range −65°C to +150°C Per MIL-STD 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Stresses at or above those listed under Absolute Maximum
ESD CAUTION
Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 10 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide