Datasheet AD9371 (Analog Devices)

Integrated, Dual RF Transceiver with Observation Path Data Sheet AD9371 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual differential transmitters (Tx) AD9371 RX1+ RX1 Dual differential receivers (Rx) DECIMATION, RX1– LPF RX2 pFIR, Observation receiver (ORx) with 2 inputs DC OFFSET RX2+ ADC QEC, 204B D Sniffer receiver (SnRx) with 3 inputs TUNING, S RX2– LPF RSSI, JE OVERLOAD Tunable range: 300 MHz to 6000 MHz ADC MICRO- Tx synthesis bandwidth (BW) to 250 MHz CONTROLLER RX_EXTLO+ LO RF Rx BW: 8 MHz to 100 MHz RX_EXTLO– GENERATOR SYNTHESIZER EXTERNAL OPTION Supports frequency division duplex (FDD) and time division TX1+ TX1 SPI duplex (TDD) operation PORT SPI TX1– LPF TX2 Fully integrated independent fractional-N radio frequency (RF) TX2+ DAC synthesizers for Tx, Rx, ORx, and clock generation pFIR, TX2– LPF QEC, 204B D INTERPOLATION JESD204B digital interface DAC S JE APPLICATIONS TX_EXTLO+ LO RF TX_EXTLO– GENERATOR SYNTHESIZER EXTERNAL GPIO I/F L 3G/4G micro and macro base stations (BTS) OPTION AUXADC R AUXDAC T LO C 3G/4G multicarrier picocells GENERATOR FDD and TDD active antenna systems +, – RF SYNTHESIZER IN IN _ Microwave, nonline of sight (NLOS) backhaul systems K K_ CLOCK L GENERATOR CL OBSERVATION C _ Rx V GENERAL DESCRIPTION ORX1+ EV_ E D D ORX1–
The AD9371 is a highly integrated, wideband RF transceiver
ORX2+ ORX2–
offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC
SNIFFER SNRXA+ Rx LPF DECIMATION,
delivers a versatile combination of high performance and low
SNRXA– pFIR, ADC AGC, SNRXB+
power consumption required by 3G/4G micro and macro BTS
DC OFFSET, 204B D SNRXB– LPF QEC, S TUNING,
equipment in both FDD and TDD applications. The AD9371
SNRXC+ ADC JE RSSI, SNRXC– OVERLOAD
operates from 300 MHz to 6000 MHz, covering most of the 1 licensed and unlicensed cellular bands. The IC supports receiver 00 1-
NOTES 1. FOR JESD204B PINS, SEE FIGURE 4.
bandwidths up to 100 MHz. It also supports observation receiver 1465 Figure 1. and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms. The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four The transceiver consists of wideband direct conversion signal lanes are dedicated to the receiver and observation receiver channels. paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, The fully integrated phase-locked loops (PLLs) provide high quadrature error correction (QEC), and programmable digital performance, low power fractional-N frequency synthesis for filters, eliminating the need for these functions in the digital the transmitter, the receiver, the observation receiver, and the baseband. Several auxiliary functions such as an auxiliary analog- clock sections. Careful design and layout techniques provide the to-digital converter (ADC), auxiliary digital-to-analog converters isolation demanded in high performance base station applications. (DACs), and general-purpose input/outputs (GPIOs) are integrated All voltage controlled oscillator (VCO) and loop filter components to provide additional monitoring and control capability. are integrated to minimize the external component count. An observation receiver channel with two inputs is included to A 1.3 V supply is required to power the core of the AD9371, and monitor each transmitter output and implement interference a standard 4-wire serial port controls it. Other voltage supplies mitigation and calibration applications. This channel also connects provide proper digital interface levels and optimize transmitter to three sniffer receiver inputs that can monitor radio activity in and auxiliary converter performance. The AD9371 is packaged in a different bands. 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
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Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL External LO Inputs Serial Peripheral Interface (SPI) Interface GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence JTAG Boundary Scan Outline Dimensions Ordering Guide