Datasheet AD9371 (Analog Devices) - 10

AD9371 Data Sheet Parameter Min Typ Max Unit Test Conditions / Comments
POSITIVE SUPPLY CURRENT (Tx MODE) Two Tx channels enabled, Rx downconverter disabled, 200 MHz Tx BW, 245.76 MSPS data rate (ORx disabled) VDDA_1P3 Analog Supplies1 1000 mA VDIG Supply 410 mA Tx QEC2 active VDDA_1P8 Supply Full-scale CW3 405 mA Tx RF attenuation = 0 dB, 80 mA Tx RF attenuation = 15 dB VDD_IF Supply 8 mA VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA VDDA_SER, VDDA_DES, 375 mA JESD_VTT_DES Supplies Total Power Dissipation Typical supply voltages, Tx QEC2 active 3.70 W Tx RF attenuation = 0 dB 3.11 W Tx RF attenuation = 15 dB POSITIVE SUPPLY CURRENT (FDD MODE), 100 MHz Rx BW, 122.88 MSPS data rate; 200 MHz Tx BW, 2× Rx, 2× Tx, ORx ACTIVE 245.76 MSPS data rate; 200 MHz ORx BW, 245.76 MSPS data rate VDDA_1P3 Analog Supplies1 1700 mA VDIG Supply 1080 mA Tx QEC2 active VDDA_1P8 Supply Full-scale CW3 405 mA Tx RF attenuation = 0 dB 80 mA Tx RF attenuation = 15 dB VDD_IF Supply 8 mA VDDA_3P3 Supply 2 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA VDDA_SER, VDDA_DES, 375 mA JESD_VTT_DES Supplies Total Power Dissipation Typical supply voltages, Tx QEC2 active 4.86 W Tx RF attenuation = 0 dB 4.27 W Tx RF attenuation = 15 dB MAXIMUM OPERATING JUNCTION 110 °C Device designed for 10-year lifetime when operating at TEMPERATURE maximum junction temperature 1 VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. 2 QEC is the system for minimizing quadrature images of a desired signal. 3 Continuous wave (CW) is a single frequency signal.
TIMING SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SERIAL PERIPHERAL INTERFACE (SPI) TIMING SCLK Period tCP 20 ns SCLK Pulse Width tMP 10 ns CSB Setup to First SCLK Rising Edge tSC 3 ns Last SCLK Falling Edge to CSB Hold tHC 0 ns SDIO Data Input Setup to SCLK tS 2 ns SDIO Data Input Hold to SCLK tH 0 ns SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode) tCO 3 8 ns Bus Turnaround Time After Baseband Processor (BBP) Drives tHZM tH tCO ns Last Address Bit Bus Turnaround Time After AD9371 Drives Last Address Bit tHZS 0 tCO ns DIGITAL TIMING TXx_ENABLE Pulse Width 10 μs RXx_ENABLE Pulse Width 10 μs Rev. B | Page 10 of 57 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL External LO Inputs Serial Peripheral Interface (SPI) Interface GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence JTAG Boundary Scan Outline Dimensions Ordering Guide