Datasheet ADRV9026 (Analog Devices) - 4

ADRV9026 Data Sheet SPECIFICATIONS
Electrical characteristics at ambient temperature range. Power supplies are as follows: VDDA_1P8 = 1.8 V, VIF = 1.8 V, VDDA_1P3 = 1.3 V, VDDA_1P0 = 1.0 V, and VDIG_1P0 = 1.0 V. VDDA_1P8 represents VCONV1_1P8, VCONV2_1P8, VANA1_1P8, VANA2_1P8, VANA3_1P8, VANA4_1P8, and VJVCO_1P8. VDDA_1P3 represents VANA1_1P3, VANA2_1P3, VCONV1_1P3, VCONV2_1P3, VRFVCO1_1P3, VRFVCO2_1P3, VAUXVCO_1P3, VCLKVCO_1P3, VRFSYN1_1P3, VRFSYN2_1P3, VCLKSYN_1P3, VAUXSYN_1P3, VRXLO_1P3, and VTXLO_1P3. VDDA_1P0 represents VJSYN_1P0, VDES_1P0, VTT_DES, and VSER_1P0. All RF specifications are based on measurements that include printed circuit board (PCB) and matching circuit losses, unless otherwise noted. Device configuration profile: Receiver = 200 MHz bandwidth, I/Q rate = 245.76 MHz, transmitter = 200 MHz large signal bandwidth plus 450 MHz synthesis bandwidth, I/Q rate = 491.52 MHz, observation receiver (ORX) = 450 MHz bandwidth, I/Q rate = 491.52 MHz, device clock = 245.76 MHz, unless otherwise noted. Note: if signals are placed outside of the primary bandwidth, degradation in linearity, image rejection, and flatness may be observed.
TRANSMITTERS AND RECEIVERS Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTERS Tx Center Frequency 650 6000 MHz Tx Synthesis Bandwidth 450 MHz Tx Large Signal Bandwidth 200 MHz Zero intermediate frequency (IF) mode Peak-to-Peak Gain Deviation 1.0 dB 450 MHz bandwidth, includes compensation by programmable finite impulse response (FIR) filter 0.1 dB Any 20 MHz bandwidth span, includes compensation by programmable FIR filter (pFIR) Deviation from Linear Phase 1 Degrees 450 MHz bandwidth Maximum Output Power 0 dBFS, 1 MHz signal input, 50 Ω load, 0 dB transmitter attenuation 800 MHz 6.7 dBm 1800 MHz 6.6 dBm 2600 MHz 6.3 dBm 3800 MHz 6.4 dBm 4800 MHz 6.1 dBm 5700 MHz 6.4 dBm Power Control Range 32 dB Power Control Resolution 0.05 dB Attenuation Accuracy Integral Nonlinearity (Gain) INL 0.1 dB Valid over full power control range for any 4 dB step Differential Nonlinearity (Gain) DNL ±0.04 dB Monotonic Output Power Temperature −4.5 mdB/°C Valid over full power control range Slope LO Delay Temperature Slope 1.05 ps/°C Valid over full power control range Adjacent Channel Leakage Power 20 MHz LTE at −12 dBFS Ratio (ACLR) Long Term Evolution (LTE) 800 MHz −68 dB 1800 MHz −67 dB 2600 MHz −66 dB 3800 MHz −65 dB 4800 MHz −65 dB 5700 MHz −65 dB Rev. A | Page 4 of 118 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Transmitters and Receivers Synthesizers, Auxiliary Converters, and Clock References Digital Specifications Power Supply Specifications Current Consumption TDD Operation—Four Receiver Channels Enabled TDD Operation—Four Transmitter and One Observation Receiver Channels Enabled FDD Operation—LO1 and LO2, Four Receiver, Four Transmitter, and One Observation Receiver Channels Enabled Digital Interface and Timing Specifications Absolute Maximum Ratings Junction Temperature Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Band 1800 MHz Band 2600 MHz Band 3800 MHz Band 4800 MHz Band 5700 MHz Band Theory of Operation General Transmitter Receiver Observation Receiver Clock Input Synthesizers RF Synthesizers Auxiliary Synthesizer Clock Synthesizer SPI Interface GPIO_x Pins Auxiliary Converters GPIO_ANA_x/AUXDAC_x AUXADC_x JTAG Boundary Scan Applications Information Power Supply Sequence Data Interface Outline Dimensions Ordering Guide