Datasheet ADL5920 (Analog Devices) - 9

FabricanteAnalog Devices
Descripción9 kHz to 7 GHz, Bidirectional RMS and VSWR Detector
Páginas / Página26 / 9 — Data Sheet. ADL5920. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. FIN. …
RevisiónB
Formato / tamaño de archivoPDF / 808 Kb
Idioma del documentoInglés

Data Sheet. ADL5920. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. FIN. ND6. ND5. ND4. ND3. GND1 1. 24 GND2. VNEG1 2. 23 VNEG2. CHPR+ 3. 22 CHPF–

Data Sheet ADL5920 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FIN ND6 ND5 ND4 ND3 GND1 1 24 GND2 VNEG1 2 23 VNEG2 CHPR+ 3 22 CHPF–

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Data Sheet ADL5920 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS UT UT O O FIN FIN ND6 ND5 ND4 ND3 R R G G G G RF RF 32 31 30 29 28 27 26 25 GND1 1 24 GND2 VNEG1 2 23 VNEG2 CHPR+ 3 22 CHPF– ADL5920 CHPR– 4 21 CHPF+ TOP VIEW PWDN/TADJS 5 20 TADJI (Not to Scale) VTEMP 6 19 VREF VRMSR 7 18 VRMSF VPOS1 8 17 VPOS3 9 1 10 1 12 13 14 15 16 R L F S CM C S2 S O IFF– IFF+ TGT V D DE D V CRM V VPO V CRM NOTES
002
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A GROUND PLANE WITH LOW THERMAL AND ELECTRICAL IMPEDANCE.
16085- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 24, 27 to 30 GND1, GND2, GND3, RF Ground. Connect all ground pins to a low impedance ground plane. GND4, GND5, GND6 2, 23 VNEG1, VNEG2 Negative Supply Pins. For normal single-supply operation, connect these pins to ground. In applications where the RF input and output are dc-coupled, apply a −2.5 V supply voltage to these pins along with a +5 V power supply on VPOS1, VPOS2, and VPOS3. In this dc-coupled operating mode, Pin 12 (DECL) must be connected to ground. 8, 13, 17 VPOS1, VPOS2, VPOS3 Power Supply. Separately decouple each power supply pin using 100 pF and 0.1 µF capacitors. The nominal supply voltage on these pins is 5 V. 3, 4, 21, 22 CHPR+, CHPR−, CHPF+, CHPF− Offset Compensation Loop Control. The capacitances on these pin pairs set the high- pass corner frequency of the internal offset compensation loops, which in turn sets the minimum operating frequency of the rms detectors in the forward and reverse paths. For normal operation, add a capacitor from each pin to ground along with a capacitor across the pins. To operate at input frequencies down to 9 kHz, capacitances in the 1 µF range are required. To maintain the specified directivity, leave these pins open when operating at frequencies above 2 GHz. 5 PWDN/TADJS Temperature Compensation and Shutdown. This pin is a dual function pin that controls temperature slope compensation at voltages <1.0 V and/or shuts down the device at voltages >1.4 V. The temperature compensation voltage is set by connecting this pin to VREF through a resistor divider. 6 VTEMP Temperature Sensor Output of 1.38 V at TA = 25°C with a Coefficient of 4.5 mV/°C. 7, 18 VRMSR, VRMSF Reverse and Forward RMS Voltage Measurement. The voltages on these pins are proportional to the decibel power of the incident signal to the RFOUT and RFIN pins. 9, 16 CRMSR, CRMSF RMS Averaging Capacitor for Reverse and Forward Path Detectors. Connect rms averaging capacitors between CRMSR and ground and between CRMSF and ground to set the averaging time constant of the forward and reverse rms detectors. For normal operation, the values of these two capacitors must be equal. 10 VOCM Common-Mode Input Voltage for VDIFF+ and VDIFF−. The input voltage applied to VOCM sets the common-mode voltage for the VDIFF+ and VDIFF− differential pair. The nominal voltage on this pin is 2.5 V. However, this value can be reduced to as low as 1.5 V to accommodate the common-mode requirements of the ADC, which is driven by VDIFF+ and VDIFF−. The VOCM input requires a bias current of ±1 mA and must be driven from a low impedance source. VOCM can be driven from the VREF pin but the connection must include a 1 kΩ resistor to ground. 11, 14 VDIFF−, VDIFF+ Return Loss and VSWR Output. The differential voltage on these pins is proportional to the dB return loss of the load connected to the RFOUT port when the device is driven through the RFIN port. This differential voltage has a bias level equal to the voltage applied to VOCM, nominally 2.5 V. Rev. B | Page 9 of 26 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Basic Connections CHPR± and CHPF± Capacitors VREF Interface VDIFF Output Interface Temperature Drift Compensation Setting VTGT Choosing Values for CRMSF and CRMSR RF Power and Return Loss Calculation DC-Coupled Operation Evaluation Board Outline Dimensions Ordering Guide