Datasheet LTM8025 (Analog Devices) - 8

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PIN FUNCTIONS VOUT (Bank 1):
Power Output Pins. Apply the output filter
RUN/SS (Pin L5):
Pull the RUN/SS pin below 0.2V to capacitor and the output load between these pins and shut down the LTM8025. Tie to 2.5V or more for normal GND pins. operation. If the shutdown feature is not used, tie this pin
GND (Bank 2):
Tie these GND pins to a local ground to the VIN pin. RUN/SS also provides a soft-start function; plane below the LTM8025 and the circuit components. see the Applications Information section. In most applications, the bulk of the heat flow out of the
SYNC (Pin L6):
This is the external clock synchronization LTM8025 is through these pads, so the printed circuit input. Ground this pin for low ripple Burst Mode operation design has a large impact on the thermal performance of at low output loads. Tie to a stable voltage source greater the part. See the PCB Layout and Thermal Considerations than 0.7V to disable Burst Mode operation. Do not leave sections for more details. Return the feedback divider this pin floating. Tie to a clock source for synchroniza- (RADJ) to this net. tion. Clock edges should have rise and fall times faster
V
than 1μs. See the Synchronization section in Applications
IN (Bank 3):
The VIN pin supplies current to the LTM8025’s internal regulator and to the internal power switch. This Information. pin must be locally bypassed with an external, low ESR
RT (Pin G7):
The RT pin is used to program the switching capacitor; see Table 1 for recommended values. frequency of the LTM8025 by connecting a resistor from
AUX (Pin G5):
Low Current Voltage Source for BIAS. In this pin to ground. Table 2 gives the resistor values that many designs, the BIAS pin is simply connected to V correspond to the resultant switching frequency. Minimize OUT. The AUX pin is internally connected to V the capacitance at this pin. OUT and is placed adjacent to the BIAS pin to ease printed circuit board rout-
SHARE (Pin H7):
Tie this to the SHARE pin of another ing. Although this pin is internally connected to VOUT, it LTM8025 when paralleling the outputs. Otherwise, do not is not intended to deliver a high current, so do
not
draw connect. current from this pin to the load. If this pin is not tied to
PGOOD (Pin J7):
The PGOOD pin is the open-collector BIAS, leave it floating. output of an internal comparator. PGOOD remains low
BIAS (Pin H5):
The BIAS pin connects to the internal until the ADJ pin is within 10% of the final regulation power bus. Connect to a power source greater than 2.8V voltage. PGOOD output is valid when VIN is above 3.6V and less than 25V. If the output is greater than 2.8V, con- and RUN/SS is high. If this function is not used, leave nect this pin there. If the output voltage is less, connect this pin floating. this to a voltage source between 2.8V and 25V. Also, make
ADJ (Pin K7):
The LTM8025 regulates its ADJ pin to sure that BIAS + VIN is less than 56V. 0.79V. Connect the adjust resistor from this pin to ground. The value of RADJ is given by the equation RADJ = 394.21/ (VOUT – 0.79), where RADJ is in kΩ. Rev. D 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Package Photography Typical Application Related Parts