Data SheetADuM5210/ADuM5211/ADuM5212SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25°C, VDD1 = VDD2 = VDDP = 5 V, VSEL resistor network: R1 = 10 kΩ, R2 = 30.9 kΩ between VISO and GNDISO. Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1, VDD2, VDDP ≤ 5.5 V and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 3. DC-to-DC Converter Static Specifications Parameter SymbolMinTypMaxUnitTestConditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint VISO 4.675 5.0 5.325 V IISO = 15 mA, R1 = 10 kΩ, R2 = 30.9 kΩ Thermal Coefficient VISO (TC) −44 μV/°C Line Regulation VISO (LINE) 20 mV/V IISO = 15 mA, VDDP = 4.5 V to 5.5 V Load Regulation VISO (LOAD) 1.3 3 % IISO = 3 mA to 27 mA Output Ripple VISO (RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 27 mA Output Noise VISO (NOISE) 200 mV p-p CBO = 0.1 μF||10 μF, IISO = 27 mA Switching Frequency fOSC 125 MHz Pulse-Width Modulation fPWM 600 kHz Frequency Output Supply IISO (MAX) 30 mA 5.5 V > VISO > 4.5 V Efficiency at IISO (MAX) 29 % IISO = 27 mA IDDP, No VISO Load IDDP (Q) 6.8 12 mA IDDP, Full VISO Load IDDP (MAX) 104 mA Thermal Shutdown Shutdown Temperature 154 °C Thermal Hysteresis 10 °C Table 4. Data Channel Supply Current1 Mbps—A, B, C Grades25 Mbps—B, C Grades100 Mbps—C GradeTest Conditions/Parameter SymbolMin Typ Max Min Typ Max Min TypUnitMaxComments SUPPLY CURRENT ADuM5210 IDD1 1.1 1.6 6.2 7.0 20 25 mA CL = 0 pF IDD2 2.7 4.5 4.8 7.0 9.5 15 mA CL = 0 pF ADuM5211 IDD1 2.1 2.7 4.9 6.5 15 19 mA CL = 0 pF IDD2 2.3 2.9 4.7 6.5 15.6 19 mA CL = 0 pF ADuM5212 IDD1 2.7 4.5 4.8 7.0 9.5 15 mA CL = 0 pF IDD2 1.1 1.6 6.2 7.0 20 25 mA CL = 0 pF Table 5. Switching SpecificationsA GradeB GradeC GradeTest Conditions/Parameter SymbolMin Typ Max Min Typ Max Min TypUnitMaxComments SWITCHING SPECIFICATIONS Data Rate 1 25 100 Mbps Within PWD limit Propagation Delay tPHL, tPLH 50 35 20 23 29 ns 50% input to 50% output Pulse Width Distortion PWD 10 3 2 ns |tPLH − tPHL| Pulse Width PW 1000 40 10 ns Within PWD limit Propagation Delay Skew tPSK 38 12 9 ns Between any two units Channel Matching Codirectional tPSKCD 5 3 2 ns Opposing Direction tPSKOD 10 6 5 ns Jitter 2 2 1 ns Rev. D | Page 3 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY PACKAGE CHARACTERISTICS REGULATORY APPROVALS INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION PCB LAYOUT THERMAL ANALYSIS PROPAGATION DELAY PARAMETERS EMI CONSIDERATIONS DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY POWER CONSUMPTION INSULATION LIFETIME OUTLINE DIMENSIONS ORDERING GUIDE