Datasheet AD7292 (Analog Devices) - 6

AD7292 Data Sheet TIMING SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, CL = 27 pF, TA = −40°C to +125°C, unless otherwise noted.1
Table 5. Limit at TMIN/TMAX Parameter Description VDRIVE = 1.8 V VDRIVE = 2.7 V to 5.25 V Unit
tCONVERT ADC conversion time/BUSY high time Temperature sensor disabled 950 950 ns max Temperature sensor enabled 5.85 5.85 μs max tACQ ADC acquisition time 50 50 ns max fSCLK Frequency of serial read clock2 15 25 MHz max t1 SCLK period 66 40 ns min t2 SCLK low 33 20 ns min t3 SCLK high 33 20 ns min t4 CS falling edge to SCLK rising edge 4 4 ns min t5 DIN setup time to SCLK falling edge 4 4 ns min t 3 6 DIN hold time after SCLK falling edge 2 2 ns max t7 SCLK falling edge to CS rising edge 5 5 ns min t8 CS high 5 5 ns min t9 SCLK to output data valid delay time 30 19 ns max t10 SCLK to output data valid hold time 7 5 ns min t 4 11 CS rising edge to SCLK rising edge 4 4 ns min t12 CS rising edge to DOUT high impedance 15 15 ns max 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE). 2 For VDRIVE = 2.5 V, fSCLK = 22 MHz maximum. 3 Time required for the output to cross 0.2 × VDRIVE and 0.8 × VDRIVE when VDRIVE = 1.8 V; time required for the output to cross 0.3 × VDRIVE and 0.7 × VDRIVE when VDRIVE = 2.7 V to 5.25 V. 4 Guaranteed by design.
Timing Diagram BUSY2 t7 t8 t CS 3 t t t11 4 2 t1 SCLK t5 t6 DIN X R W D5 D4 D3 D2 D1 D0 LSB X t10 HIGH-Z HIGH-Z DOUT1 LSB t t 9 12 1PROVIDED THE READ BIT IS SET. 2IF AN ADC CONVERSION IS REQUESTED.
2
t
-00
7 = 5ns IF NO ADC CONVERSION
60
955ns WITH ADC CONVERSION
106 Figure 2. Serial Interface Timing Diagram Rev. A | Page 6 of 40 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications ADC Specifications DAC Specifications General Specifications Temperature Sensor Specifications Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs Single-Ended Mode Differential Mode ADC Transfer Functions Temperature Sensor DAC Operation Digital I/O Pins GPIO0/ALERT0 and GPIO1/ALERT1 Pins GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins GPIO3/LDAC Pin GPIO6/BUSY Pin Serial Port Interface (SPI) Interface Protocol Register Structure Register Descriptions Vendor ID Register (Address 0x00) ADC Data Register (Address 0x01) ADC Sequence Register (Address 0x03) Configuration Register Bank (Address 0x05) Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) General Subregister (Address 0x08) VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) ADC Sampling Mode Subregister (Address 0x12) VIN Filter Subregister (Address 0x13) Conversion Delay Control Subregister (Address 0x14) VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Temperature Sensor Subregister (Address 0x20) Temperature Sensor Alert Routing Subregister (Address 0x21) GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) Alert Limits Register Bank (Address 0x06) Alert High Limit and Alert Low Limit Subregisters Hysteresis Subregisters Alert Flags Register Bank (Address 0x07) ADC Alert Flags and TSENSE Alert Flags Subregisters (Address 0x00 and Address 0x02) Minimum and Maximum Register Bank (Address 0x08) Offset Register Bank (Address 0x09) DAC Buffer Enable Register (Address 0x0A) GPIO Register (Address 0x0B) Conversion Command Register (Address 0x0E) ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) TSENSE Conversion Result Register (Address 0x20) DAC Channel Registers (Address 0x30 to Address 0x33) ADC Conversion Control ADC Conversion Command ADC Sequencer DAC Output Control LDAC Operation Simultaneous Update of All DAC Outputs Alerts and Limits Alert Limit Monitoring Features Hysteresis Hardware Alert Pins Alert Flag Bits in the Conversion Result Registers Alert Flags Register Bank Minimum and Maximum Conversion Results Outline Dimensions Ordering Guide