Datasheet AD7292 (Analog Devices) - 10

AD7292 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AVDD = 5V AVDD = 5V DVDD = 5V DVDD = 5.25V –20 V –20 DRIVE = 3V VDRIVE = 1.8V TA = 25°C TA = 25°C fSAMPLE = 200kSPS fSAMPLE = 200kSPS –40 –40 B) RANGE = 0V TO V B) RANGE = 0V TO 2 × V d REF d REF ( SINGLE-ENDED MODE ( DIFFERENTIAL MODE SNR = 61.6dB SNR = 61.798dB UDE –60 THD = –84.0dB UDE –60 THD = –86.602dB IT IT L SINAD = 61.49dB L SINAD = 61.784dB P SFDR = 79.05dB P SFDR = 86.142dB AM –80 AM –80 –100 –100 –120 –120 0 10 20 30 40 50 60 70 80 90 100
004
0 10 20 30 40 50 60 70 80 90 100
005
INPUT FREQUENCY (kHz)
10660-
INPUT FREQUENCY (kHz)
10660- Figure 4. ADC FFT, 200 kSPS, fIN = 10 kHz, Single-Ended Mode Figure 7. ADC FFT, 200 kSPS, fIN = 10 kHz, Differential Mode
0.3 0.3 AVDD = DVDD = 5.25V AVDD = 4.75V TA = 25°C VDRIVE = 1.8V DVDD = 5.25V WCP INL = 0.091LSB CHANNEL 3 0.2 INTERNAL REFERENCE 0.2 VDRIVE = 3.3V WCN INL = –0.093LSB T CHANNEL 0 AND CHANNE L 1 A = 25°C WCP INL = 0.068LSB INTERNAL REFERENCE WCN INL = –0.255LSB DIFFERENTIAL MODE, 0V TO VREF RANGE 0.1 B) SINGLE-ENDED MODE, 0V TO 4 × V 0.1 REF RANGE B) S S L L R ( R ( 0 0 RRO RRO E E L L IN –0.1 IN –0.1 –0.2 –0.2 –0.3 –0.3 0 128 256 384 512 640 768 896 1024
006
0 128 256 384 512 640 768 896 1024
008
ADC CODE ADC CODE
10660- 10660- Figure 5. Typical ADC INL, Single-Ended Mode Figure 8. Typical ADC INL, Differential Mode
0.3 0.25 AVDD = DVDD = 5.25V TA = 25°C AVDD = 4.75V TA = 25°C VDRIVE = 1.8V WCP DNL = 0.11LSB 0.20 DVDD = 5.25V WCP INL = 0.067LSB 0.2 CHANNEL 3 WCN DNL = –0.119LSB VDRIVE = 3.3V WCN INL = –0.08LSB INTERNAL REFERENCE 0.15 CHANNEL 0 AND CHANNE L 1 SINGLE-ENDED MODE, 0V TO 4 × VREF RANGE INTERNAL REFERENCE 0.10 DIFFERENTIAL MODE, 0V TO VREF RANGE B) 0.1 B) S S L L 0.05 R ( R ( 0 0 RRO RRO E E L L –0.05 DN –0.1 DN –0.10 –0.15 –0.2 –0.20 –0.3 –0.25 0 128 256 384 512 640 768 896 1024
007
0 128 256 384 512 640 768 896 1024 ADC CODE
10660-
ADC CODE
10660–009 Figure 6. Typical ADC DNL, Single-Ended Mode Figure 9. Typical ADC DNL, Differential Mode Rev. A | Page 10 of 40 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications ADC Specifications DAC Specifications General Specifications Temperature Sensor Specifications Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs Single-Ended Mode Differential Mode ADC Transfer Functions Temperature Sensor DAC Operation Digital I/O Pins GPIO0/ALERT0 and GPIO1/ALERT1 Pins GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins GPIO3/LDAC Pin GPIO6/BUSY Pin Serial Port Interface (SPI) Interface Protocol Register Structure Register Descriptions Vendor ID Register (Address 0x00) ADC Data Register (Address 0x01) ADC Sequence Register (Address 0x03) Configuration Register Bank (Address 0x05) Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) General Subregister (Address 0x08) VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) ADC Sampling Mode Subregister (Address 0x12) VIN Filter Subregister (Address 0x13) Conversion Delay Control Subregister (Address 0x14) VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Temperature Sensor Subregister (Address 0x20) Temperature Sensor Alert Routing Subregister (Address 0x21) GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) Alert Limits Register Bank (Address 0x06) Alert High Limit and Alert Low Limit Subregisters Hysteresis Subregisters Alert Flags Register Bank (Address 0x07) ADC Alert Flags and TSENSE Alert Flags Subregisters (Address 0x00 and Address 0x02) Minimum and Maximum Register Bank (Address 0x08) Offset Register Bank (Address 0x09) DAC Buffer Enable Register (Address 0x0A) GPIO Register (Address 0x0B) Conversion Command Register (Address 0x0E) ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) TSENSE Conversion Result Register (Address 0x20) DAC Channel Registers (Address 0x30 to Address 0x33) ADC Conversion Control ADC Conversion Command ADC Sequencer DAC Output Control LDAC Operation Simultaneous Update of All DAC Outputs Alerts and Limits Alert Limit Monitoring Features Hysteresis Hardware Alert Pins Alert Flag Bits in the Conversion Result Registers Alert Flags Register Bank Minimum and Maximum Conversion Results Outline Dimensions Ordering Guide