Datasheet AD5940, AD5941 (Analog Devices) - 44

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AD5940/ AD5941 Data Sheet HIGH SPEED DAC CALIBRATION OPTIONS
The high speed DAC transfer function is shown in Figure 27. The high speed DAC is not calibrated during production testing Figure 28 shows how the common-mode voltage is set by the by Analog Devices. This section describes the steps to calibrate noninverting input of the high speed TIA. This voltage must be the high speed DAC for all gain settings and in both high power set by the low power DAC VZERO0 output or by the internal and low power modes. 1.11 V ADC VBIAS0 voltage.
DAC CODES OUTPUT VOLTAGE
Calibrate the high speed DAC when the DAC is needed to
0xE00
generate an excitation signal to a sensor. If an offset error exists
(POSITIVE DAC VOLTAGE = FULL SCALE) COMMON-MODE VOLTAGE
on the excitation signal, and a current or voltage output requires
POSITIVE FULL SCALE
measurement, the excitation signal can exceed the headroom of the selected TIA, ADC input buffer, or PGA setting.
OFFSET ERROR 0x800 DAC VOLTAGE =
Figure 28 shows the circuit diagram for high speed DAC
(ZERO SCALE) COMMON-MODE VOLTAGE
calibration. A precision external resistor, RCAL, is required between the RCAL0 pin and the RCAL1 pin. To calibrate the offset, the differential voltage measured across the R
0x200
CAL resistor
(NEGATIVE DAC VOLTAGE = COMMON-MODE VOLTAGE
016 must be 0 V.
FULL SCALE) NEGATIVE FULL SCALE
16778- Calibrate the high speed DAC with the required bit settings Figure 27. High Speed DAC Transfer Function (HSDACCON, Bit 12 and Bit 0). For example, if the DAC is The AD5940/AD5941 software development kit includes calibrated with HSDACCON, Bit 12 = 0 and HSDACCON, sample functions that demonstrate how to use the ADC to Bit 0 = 0, and the user changes HSDACCON, Bit 12 to 1, an measure the differential voltage across the RCAL resistor and how offset error is introduced. Either the DACOFFSET register or to adjust the appropriate calibration register until the DACOFFSETHS register must be recalibrated for the new differential voltage is ~0 V. The AD5940/AD5941 software output range. development kit is available for download from the The gain calibration is optional and adjusts the peak-to-peak AD5940/AD5941 product page. voltage swing. Alternatively, adjust the voltage swing by changing the maximum and/or minimum DAC code.
PMBW[0] PMBW[0] DACOFFSET 0 0 DACOFFSETATTEN DACOFFSETHS 1 1 DACOFFSETATTENHS VREF_1V82 G = 1 OR G = 0.2 HSDACCON[0] f 1.0V C = 50kHz/100kHz/ 250kHz HSDACCON[0] 0 1 DACGAIN P + RCAL0 D EXCITATION HIGH SPEED HSDACDAT[11:0] AMP – PGA DAC N RCF 0.2V RCAL G = 1 OR 0.25 DAC CLK HSDACCON [12] RCAL1 NEGATIVE NODE ADC MEASURES DIFFERENTIAL VOLTAGE BETWEEN P-NODES AND HSTIACON[1:0] N-NODES TO CALIBRATE DAC POSITIVE VBIAS_CAP SETS NODE (1.11V) COMMON-MODE MUX VOLTAGE NEGATIVE VZERO NODE ADC MUX TO ADC + HSTIA –
017 16778- Figure 28. High Speed DAC Calibration Rev. B | Page 44 of 133 Document Outline FEATURES APPLICATIONS SIMPLIFIED BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ADC RMS NOISE SPECIFICATIONS ADC RMS Noise: Digital Filter Settings ADC RMS Noise: Peak-to-Peak Effective Bits SPI TIMING SPECIFICATIONS SPI Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS REFERENCE TEST CIRCUIT THEORY OF OPERATION CONFIGURATION REGISTERS Configuration Register—AFECON Power Mode Configuration Register—PMBW SILICON IDENTIFICATION IDENTIFICATION REGISTERS Analog Devices, Inc., Identification Register—ADIID Chip Identification Register—CHIPID SYSTEM INITIALIZATION LOW POWER DAC LOW POWER DAC SWITCH OPTIONS RELATIONSHIP BETWEEN THE 12-BIT AND 6-BIT OUTPUTS LOW POWER DAC USE CASES Electrochemical Amperometric Measurement Electrochemical Impedance Spectroscopy Low Power DAC in 4-Wire Isolated Impedance Measurements LOW POWER DAC CIRCUIT REGISTERS LPDACCON0 Register—LPDACCON0 Low Power DAC Switch Control Register—LPDACSW0 Low Power DAC Data Output Register—LPDACDAT0 Low Power Reference Control Register—LPREFBUFCON Common-Mode Switch Mux Register—SWMUX LOW POWER POTENTIOSTAT LOW POWER TIA LOW POWER TIA PROTECTION DIODES Current-Limit Feature of the Low Power TIA and Potentiostat amplifier Low Power TIA Force/Sense Feature USING AN EXTERNAL RTIA RECOMMENDED SWITCH SETTINGS FOR VARIOUS OPERATING MODES LOW POWER TIA CIRCUITS REGISTERS Low Power TIA Switch Configuration Register—LPTIASW0 Low Power TIA Control Bits, Channel 0 Register—LPTIACON0 HIGH SPEED DAC CIRCUITS HIGH SPEED DAC OUTPUT SIGNAL GENERATION POWER MODES OF THE HIGH SPEED DAC CORE Low Power Mode High Power Mode Hibernate Mode HIGH SPEED DAC FILTER OPTIONS HIGH SPEED DAC OUTPUT ATTENUATION OPTIONS HIGH SPEED DAC EXCITATION AMPLIFIER COUPLING AN AC SIGNAL FROM THE HIGH SPEED DAC TO THE DC LEVEL SET BY THE LOW POWER DAC AVOIDING INCOHERENCY ERRORS BETWEEN EXCITATION AND MEASUREMENT FREQUENCIES DURING IMPEDANCE MEASUREMENTS HIGH SPEED DAC CALIBRATION OPTIONS HIGH SPEED DAC CIRCUIT REGISTERS High Speed DAC Configuration Register—HSDACCON High Speed DAC Code Register—HSDACDAT Calibration Data Lock Register—CALDATLOCK DAC Gain Register—DACGAIN DAC Offset with Attenuator Enabled (Low Power Mode) Register—DACOFFSETATTEN DAC Offset with Attenuator Disabled (Low Power Mode Register)—DACOFFSET DAC Offset with Attenuator Enabled (High Speed Mode Register)—DACOFFSETATTENHS DAC Offset with Attenuator Disabled (High Speed Mode Register)—DACOFFSETHS HIGH SPEED TIA CIRCUITS HIGH SPEED TIA CONFIGURATION Input Signal Selection Gain Resistor Selection Load Resistor Selection Common-Mode Voltage Selection External RTIA Selection HIGH SPEED TIA CIRCUIT REGISTERS High Speed RTIA Configuration Register—HSRTIACON DE0 High Speed TIA Resistors Configuration Register—DE0RESCON High Speed TIA Configuration Register—HSTIACON HIGH PERFORMANCE ADC CIRCUIT ADC CIRCUIT OVERVIEW ADC CIRCUIT DIAGRAM ADC CIRCUIT FEATURES ADC CIRCUIT OPERATION ADC TRANSFER FUNCTION ADC LOW POWER CURRENT INPUT CHANNEL SELECTING INPUTS TO ADC MUX ADC POSTPROCESSING Sinc3 Filter INTERNAL TEMPERATURE SENSOR CHANNEL SINC2 FILTER (50 HZ/60 HZ MAINS FILTER) ADC CALIBRATION ADC CIRCUIT REGISTERS ADC Output Filters Configuration Register—ADCFILTERCON ADC Raw Result Register—ADCDAT DFT Result, Real Device Register—DFTREAL DFT Result, Imaginary Device Register—DFTIMAG Sinc2 Filter Result Register—SINC2DAT Temperature Sensor Result Register—TEMPSENSDAT DFT Configuration Register—DFTCON Temperature Sensor Configuration Register—TEMPSENS ADC Configuration Register—ADCCON Repeat ADC Conversions Control Register—REPEATADCCNV ADC Buffer Configuration Register—ADCBUFCON ADC CALIBRATION REGISTERS Calibration Data Lock Register—CALDATLOCK ADC Offset Calibration on the Low Power TIA Channel Register—ADCOFFSETLPTIA ADC Gain Calibration for the Low Power TIA Channel Register—ADCGNLPTIA ADC Offset Calibration on the High Speed TIA Channel Register—ADCOFFSETHSTIA ADC Gain Calibration for the High Speed TIA Channel Register—ADCGAINHSTIA ADC Offset Calibration Auxiliary Channel (PGA Gain = 1) Register—ADCOFFSETGN1 ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 1) Register—ADCGAINGN1 ADC Offset Calibration Auxiliary Input Channel (PGA Gain = 1.5) Register—ADCOFFSETGN1P5 ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 1.5) Register—ADCGAINGN1P5 ADC Offset Calibration Auxiliary Input Channel (PGA Gain = 2) Register—ADCOFFSETGN2 ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 2) Register—ADCGAINGN2 ADC Offset Calibration Auxiliary Input Channel (PGA Gain = 4) Register—ADCOFFSETGN4 ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 4) Register—ADCGAINGN4 ADC Offset Calibration Auxiliary Input Channel (PGA Gain = 9) Register—ADCOFFSETGN9 ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 9) Register—ADCGAINGN9 ADC Offset Calibration Temperature Sensor Channel Register—ADCOFFSETTEMPSENS ADC Gain Calibration Temperature Sensor Channel Register—ADCGAINTEMPSENS ADC DIGITAL POSTPROCESSING REGISTERS (OPTIONAL) ADC Minimum Value Check Register—ADCMIN ADC Minimum Hysteresis Value Register—ADCMINSM ADC Maximum Value Check Register—ADCMAX ADC Maximum Hysteresis Value Register—ADCMAXSMEN ADC Delta Value Check Register—ADCDELTA ADC STATISTICS REGISTERS Variance Output Register—STATSVAR Statistics Control Register—STATSCON Statistics Mean Output Register—STATSMEAN PROGRAMMABLE SWITCH MATRIX SWITCH DESCRIPTIONS Dx/DR0 Switches Px/Pxx Switches Nx/Nxx Switches Tx/TR1 Switches AFEx Switches RECOMMENDED CONFIGURATION IN HIBERNATE MODE OPTIONS FOR CONTROLLING ALL SWITCHES PROGRAMMABLE SWITCHES REGISTERS Switch Matrix Configuration Register—SWCON Switch Matrix Full Configuration Dx/DR0 Register—DSWFULLCON Switch Matrix Full Configuration Nx/Nxx Register—NSWFULLCON Switch Matrix Full Configuration Px/Pxx Register—PSWFULLCON Switch Matrix Full Configuration Tx/TR1 Register—TSWFULLCON Switch Matrix Status Dx/DR0 Register—DSWSTA Switch Matrix Status Px/Pxx Register—PSWSTA Switch Matrix Status Nx/Nxx Register—NSWSTA Switch Matrix Status Tx/TR1 Register—TSWSTA PRECISION VOLTAGE REFERENCES HIGH POWER AND LOW POWER BUFFER CONTROL REGISTER—BUFSENCON SEQUENCER SEQUENCER FEATURES SEQUENCER OVERVIEW SEQUENCER COMMANDS Write Command Timer Command SEQUENCER OPERATION Command Memory Loading Sequences Data FIFO Data FIFO Word Format Sequencer and the Sleep and Wake-Up Timer Configuring the GPIOx Pin Mux Sequencer Conflicts SEQUENCER AND FIFO REGISTERS Sequencer Configuration Register—SEQCON FIFO Configuration Register—FIFOCON Sequencer CRC Value Register—SEQCRC Sequencer Timeout Counter Register—SEQTIMEOUT Data FIFO Read Register—DATAFIFORD Command FIFO Write Register—CMDFIFOWRITE Sequencer Sleep Control Lock Register—SEQSLPLOCK Sequencer Trigger Sleep Register—SEQTRGSLP Sequence 0 Information Register—SEQ0INFO Sequence 2 Information Register—SEQ2INFO Command FIFO Write Address Register—CMDFIFOWADDR Command Data Control Register—CMDDATACON Data FIFO Threshold Register—DATAFIFOTHRES Sequence 3 Information Register—SEQ3INFO Sequence 1 Information Register—SEQ1INFO Command and Data FIFO Internal Data Count Register—FIFOCNTSTA Sync External Devices Register—SYNCEXTDEVICE Trigger Sequence Register—TRIGSEQ WAVEFORM GENERATOR WAVEFORM GENERATOR FEATURES WAVEFORM GENERATOR OPERATION Sinusoid Generator Trapezoid Generator USING THE WAVEFORM GENERATOR WITH THE LOW POWER DAC WAVEFORM GENERATOR REGISTERS Waveform Generator Configuration Register—WGCON Waveform Generator, Trapezoid DC Level 1 Register—WGDCLEVEL1 Waveform Generator, Trapezoid DC Level 2 Register—WGDCLEVEL2 Sequencer Command Count Register—SEQCNT Waveform Generator, Trapezoid Delay 1 Time Register—WGDELAY1 Waveform Generator, Trapezoid Slope 1 Time Register—WGSLOPE1 Waveform Generator, Trapezoid Delay 2 Time Register—WGDELAY2 Waveform Generator, Trapezoid Slope 2 Time Register—WGSLOPE2 Waveform Generator, Sinusoid Frequency Control Word Register—WGFCW Waveform Generator, Sinusoid Phase Offset Register—WGPHASE Waveform Generator, Sinusoid Offset Register—WGOFFSET Waveform Generator, Sinusoid Amplitude Register—WGAMPLITUDE SPI INTERFACE OVERVIEW SPI PINS Chip Select Enable SCLK MOSI and MISO SPI OPERATION COMMAND BYTE WRITING TO AND READING FROM REGISTERS READING DATA FROM THE DATA FIFO Read Data from Data FIFO SLEEP AND WAKE-UP TIMER SLEEP AND WAKE-UP TIMER FEATURES SLEEP AND WAKE-UP TIMER OVERVIEW CONFIGURING A DEFINED SEQUENCE ORDER RECOMMENDED SLEEP AND WAKE-UP TIMER OPERATION SLEEP AND WAKE-UP TIMER REGISTERS Timer Control Register—CON Order Control Register—SEQORDER Sequence 0 to Sequence 3 Wake-Up Time Registers (LSB)—SEQxWUPL Sequence 0 to Sequence 3 Wake-Up Time Registers (MSB)—SEQxWUPH Sequence 0 to Sequence 3 Sleep Time Registers (LSB)—SEQxSLEEPL Sequence 0 to Sequence 3 Sleep Time Registers (MSB)—SEQxSLEEPH Timer Wake-Up Configuration Register—TMRCON INTERRUPTS INTERRUPT CONTROLLER INTERUPTS CONFIGURING THE INTERRUPTS CUSTOM INTERRUPTS EXTERNAL INTERRUPT CONFIGURATION INTERRUPT REGISTERS Interrupt Polarity Register—INTCPOL Interrupt Clear Register—INTCCLR Interrupt Controller Select Registers—INTCSEL0 and INTCSEL1 Interrupt Controller Flag Registers—INTCFLAG0 and INTCFLAG1 Analog Generation Interrupt Register—AFEGENINTSTA EXTERNAL INTERRUPT CONFIGURATION REGISTERS External Interrupt Configuration 0 Register—EI0CON External Interrupt Configuration 1 Register—EI1CON External Interrupt Configuration 2 Register—EI2CON External Interrupt Clear Register—EICLR DIGITAL INPUTS/OUTPUTS DIGITAL INPUTS/OUTPUTS FEATURES DIGITAL INPUTS/OUTPUTS OPERATION Input/Output Pull-Up Enable Input/Output Data Input Input/Output Data Output Bit Set Bit Clear Bit Toggle Input/Output Data Output Enable Interrupt Inputs Interrupt Outputs Digital Port Multiplex GPIOx Control with the Sequencer GPIO REGISTERS GPIO Port 0 Configuration Register—GP0CON GPIO Port 0 Output Enable Register—GP0OEN GPIO Port 0 Pull-Up and Pull-Down Enable Register—GP0PE GPIO Port 0 Input Path Enable Register—GP0IEN GPIO Port 0 Registered Data Input—GP0IN GPIO Port 0 Data Output Register—GP0OUT GPIO Port 0 Data Out Set Register—GP0SET GPIO Port 0 Data Out Clear Register—GP0CLR GPIO Port 0 Pin Toggle Register—GP0TGL SYSTEM RESETS ANALOG DIE RESET REGISTERS Key Protection for the RSTCON Register—RSTCONKEY Software Reset Register—SWRSTCON Reset Status Register—RSTSTA POWER MODES ACTIVE HIGH POWER MODE (>80 kHz) ACTIVE LOW POWER MODE (<80 kHz) HIBERNATE MODE SHUTDOWN MODE LOW POWER MODE POWER MODES REGISTERS Power Modes Register—PWRMOD Key Protection for the PWRMOD Register—PWRKEY Low Power Mode AFE Control Lock Register—LPMODEKEY Low Power Mode Clock Select Register—LPMODECLKSEL Low Power Mode Configuration Register—LPMODECON CLOCKING ARCHITECTURE CLOCK FEATURES CLOCK ARCHITECTURE REGISTERS Key Protection Register for the CLKCON0 Register—CLKCON0KEY Clock Divider Configuration Register—CLKCON0 Clock Select Register—CLKSEL Clock Enable for Low Power TIA Chop and Wake-Up Timer—CLKEN0 Clock Gate Enable Register—CLKEN1 Key Protection for the OSCCON Register—OSCKEY Oscillator Control Register—OSCCON High Power Oscillator Configuration Register—HSOSCCON Key Protection for RSTCON Register—RSTCONKEY Internal Low Frequency Oscillator Register—LOSCTST APPLICATIONS INFORMATION EDA BIOIMPEDANCE MEASUREMENT USING A LOW BANDWIDTH LOOP BODY IMPEDANCE ANALYSIS (BIA) MEASUREMENT USING A HIGH BANDWIDTH LOOP HIGH PRECISION POTENTIOSAT CONFIGURATION USING THE AD5940/AD5941, AD8232, AND AD8233 FOR BIOIMPEDANCE AND ELECTROCARDIOGRAM (ECG) MEASUREMENTS SMART WATER/LIQUID QUALITY AFE OUTLINE DIMENSIONS ORDERING GUIDE