Datasheet ADP1071-1, ADP1071-2 (Analog Devices) - 9

FabricanteAnalog Devices
DescripciónIsolated Synchronous Flyback Controller with Integrated iCoupler
Páginas / Página27 / 9 — Data Sheet. ADP1071-1. /ADP1071-2. PIN CONFIGURATIONS AND FUNCTION …
RevisiónB
Formato / tamaño de archivoPDF / 577 Kb
Idioma del documentoInglés

Data Sheet. ADP1071-1. /ADP1071-2. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. GATE. GATE 1. 16 SR. AGND1. AGND1 2. 15 AGND2. VREG1

Data Sheet ADP1071-1 /ADP1071-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GATE GATE 1 16 SR AGND1 AGND1 2 15 AGND2 VREG1

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Data Sheet ADP1071-1 /ADP1071-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GATE GATE 1 16 SR 1 16 SR AGND1 AGND1 2 15 AGND2 2 15 AGND2 VREG1 VREG1 3 14 VREG2 3 14 VREG2 ADP1071-1 ADP1071-2 MODE VIN 4 13 VDD2 4 13 VDD2 TOP VIEW TOP VIEW EN EN 5 (Not to Scale) 12 OVP 5 (Not to Scale) 12 OVP CS CS 6 11 FB 6 11 FB RT RT 7 10 COMP 7 10 COMP
003 6-
SYNC
-002
SYNC 8 9 SS2 8 9 SS2
626 1562 15 Figure 2. ADP1071-1 SOIC_W Pin Configuration Figure 3. ADP1071-2 SOIC_W Pin Configuration
Table 9. Pin Function Descriptions, Wide-Body SOIC Pin No. ADP1071-1 ADP1071-2 M nemonic Description
1 1 GATE Driver Output for the Main Power MOSFET on the Primary Side. GATE is a multiple function pin. Connect a resistor from GATE to AGND1 to set up the open loop soft start time. 2 2 AGND1 Ground for the Primary Side. 3 3 VREG1 8 V Regulated Low Dropout (LDO) Output for the MOSFET Driver. Connect 1 μF or greater from VREG1 to AGND1. 4 Not MODE Light Load Mode Pin. ADP1071-1 Only. This pin sets the light load mode threshold. Connect applicable MODE to AGND1 to enable forced continuous conduction mode (CCM), or to a high logic (2.5 V or higher) to force an LLM operation, or to a resistor to set up an LLM threshold voltage. Not 4 VIN Input Voltage (ADP1071-2 Only). See the Primary Side Supply, Input Voltage, and LDO section. applicable Connect a 4.7 μF capacitor to this pin. The size of this capacitor can be reduced if the input voltage to this pin is guaranteed stable. Reference this pin to AGND1. 5 5 EN Precision Enable Input. The controller is enabled when EN is above the EN threshold voltage. This pin also has a programmable EN hysteresis. This pin is referenced to AGND1. 6 6 CS Input Current Sensing. This pin senses the input PWM current. Place a current sense resistor between the source terminal of the power MOSFET and AGND1. This current sense resistor sets up the input current limit. This pin is also used for the external slope compensator. Connect a resistor from CS to the current sense resistor to generate a voltage ramp for the slope compensation. Reference this pin to AGND1. Connect a 33 pF to 100 pF capacitor at this pin to act as a resistor capacitor (RC) filter along with the slope compensation resistor in noisy environments. 7 7 RT Switching Period Resistor. Connect a resistor from RT to AGND1 to set the oscillator frequency. 8 8 SYNC Frequency Synchronization. Connect an external clock to the SYNC pin to synchronize the internal oscillator to this external clock frequency. Connect SYNC to AGND1 if this feature is not used. It is recommended that the SYNC frequency be within 10% of the frequency set by the RT pin. 9 9 SS2 Soft Start on the Secondary Side. Connect a capacitor from SS2 to AGND2 to set up the soft start time on the secondary side. 10 10 COMP Compensation Node on the Secondary Side. This pin is the output of the transconductance (gm) amplifier. Reference this pin to AGND2. 11 11 FB Feedback Node on the Secondary Side. Set up the resistive divider from the output voltage such that the nominal voltage, when the power supply is in regulation, is 1.2 V. Reference this pin to AGND2. 12 12 OVP Output Overvoltage Protection. The OVP threshold is set at 1.36 V. Connect a resistive divider from OVP to the output and AGND2. 13 13 VDD2 Input Supply on the Secondary Side. Connect VDD2 to the output voltage of the power supply for a self driven configuration. Connect a 4.7 μF capacitor from VDD2 to AGND2. The size of this capacitor can be reduced if the input voltage to VDD2 is guaranteed to be stable. 14 14 VREG2 5 V Regulated LDO Output for Internal Bias and Powering of the Drivers of the Synchronous Rectifiers. Do not use VREG2 as a reference or load. Connect a 1 μF capacitor from VREG2 to AGND2. 15 15 AGND2 Analog Ground on Secondary Side. 16 16 SR Driver Output for Synchronous Rectifier MOSFET. Rev. B | Page 9 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Insulation and Safety Related Specifications Regulatory Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Detailed Block Diagram Primary Side Supply, Input Voltage, and LDO Secondary Side Supply and LDO Precision Enable Soft Start Procedure Output Voltage Sensing and Feedback Loop Compensation and Steady State Operation Slope Compensation Input/Output Current-Limit Protection Temperature Sensing Frequency Setting (RT Pin) Maximum Duty Cycle Frequency Synchronization Synchronous Rectifier (SR) Driver Output Overvoltage Protection (OVP) SR Dead Time Light Load Mode (LLM) and Continuous Conduction Mode (CCM) Soft Stop OCP/Feedback Recovery Output Voltage Tracking Remote System Reset OCP Counter External Start-Up Circuit Insulation Lifetime Layout Guidelines Applications Information Typical Application Circuits Outline Dimensions Ordering Guide