Datasheet KSZ8873MML (Microchip) - 10
| Fabricante | Microchip |
| Descripción | Integrated 3-Port 10/100 Managed Switch with PHY |
| Páginas / Página | 91 / 10 — KSZ8873MML. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. … |
| Formato / tamaño de archivo | PDF / 1.3 Mb |
| Idioma del documento | Inglés |
KSZ8873MML. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. Description. Number. Name. 2-1. [P2LED1, P2LED0] = [0, 1] — I2C slave mode
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KSZ8873MML TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1 [P2LED1, P2LED0] = [0, 1] — I2C slave mode
The external I2C master will drive the SCL clock. The KSZ8873MML device addresses are: 1011_1111 <read> 1011_1110 <write>
Interface Signals Type Description
SPIQ O Not used (tri-stated) SCL I I2C clock SDA I/O I2C data I/O SPIS_N I Not used 64 P2LED0 IPU/O
[P2LED1, P2LED0] = [1, 0] — SPI slave mode Interface Signals Type Description
SPIQ O SPI data out SCL I SPI clock SDA I SPI data in SPIS_N I SPI chip select
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM-mode
In SMI mode, the KSZ8873MML provides access to all its internal 8-bit regis- ters through its SCL_MDC and SDA_MDIO pins. In MIIM mode, the KSZ8873MML provides access to its 16-bit MIIM registers through its SDC_MDC and SDA_MDIO pins.
Note 2-1
P = power supply GND = ground I = input O = output I/O = bi-directional Ipu/O = Input with internal pull-up during reset; output pin otherwise. Ipu = Input with internal pull-up. Ipd = Input with internal pull-down. Opu = Output with internal pull-up. Opd = Output with internal pull-down. Speed: Low (100BASE-TX), High (10BASE-T) Full-Duplex: Low (full-duplex), High (half-duplex) Activity: Toggle (transmit/receive activity) Link: Low (link), High (no link) DS00002776A-page 10 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
The external I2C master will drive the SCL clock. The KSZ8873MML device addresses are: 1011_1111 <read> 1011_1110 <write>
Interface Signals Type Description
SPIQ O Not used (tri-stated) SCL I I2C clock SDA I/O I2C data I/O SPIS_N I Not used 64 P2LED0 IPU/O
[P2LED1, P2LED0] = [1, 0] — SPI slave mode Interface Signals Type Description
SPIQ O SPI data out SCL I SPI clock SDA I SPI data in SPIS_N I SPI chip select
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM-mode
In SMI mode, the KSZ8873MML provides access to all its internal 8-bit regis- ters through its SCL_MDC and SDA_MDIO pins. In MIIM mode, the KSZ8873MML provides access to its 16-bit MIIM registers through its SDC_MDC and SDA_MDIO pins.
Note 2-1
P = power supply GND = ground I = input O = output I/O = bi-directional Ipu/O = Input with internal pull-up during reset; output pin otherwise. Ipu = Input with internal pull-up. Ipd = Input with internal pull-down. Opu = Output with internal pull-up. Opd = Output with internal pull-down. Speed: Low (100BASE-TX), High (10BASE-T) Full-Duplex: Low (full-duplex), High (half-duplex) Activity: Toggle (transmit/receive activity) Link: Low (link), High (no link) DS00002776A-page 10 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service