Datasheet KSZ8873MML (Microchip) - 3
| Fabricante | Microchip |
| Descripción | Integrated 3-Port 10/100 Managed Switch with PHY |
| Páginas / Página | 91 / 3 — KSZ8873MML. Table of Contents |
| Formato / tamaño de archivo | PDF / 1.3 Mb |
| Idioma del documento | Inglés |
KSZ8873MML. Table of Contents
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 4 link to page 5 link to page 11 link to page 34 link to page 70 link to page 71 link to page 73 link to page 82 link to page 83 link to page 84 link to page 86 link to page 87 link to page 87 link to page 87 link to page 88
KSZ8873MML Table of Contents
1.0 Introduction ... 4 2.0 Pin Description and Configuration .. 5 3.0 Functional Description .. 11 4.0 Register Descriptions .. 34 5.0 Operational Characteristics ... 70 6.0 Electrical Characteristics ... 71 7.0 Timing Specifications .. 73 8.0 Reset Circuit ... 83 9.0 Selection of Isolation Transformers .. 84 10.0 Package Outline .. 85 Appendix A: Data Sheet Revision History ... 87 The Microchip Web Site .. 88 Customer Change Notification Service ... 88 Customer Support ... 88 Product Identification System ... 89 2018 Microchip Technology Inc. DS00002776A-page 3 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
KSZ8873MML Table of Contents
1.0 Introduction ... 4 2.0 Pin Description and Configuration .. 5 3.0 Functional Description .. 11 4.0 Register Descriptions .. 34 5.0 Operational Characteristics ... 70 6.0 Electrical Characteristics ... 71 7.0 Timing Specifications .. 73 8.0 Reset Circuit ... 83 9.0 Selection of Isolation Transformers .. 84 10.0 Package Outline .. 85 Appendix A: Data Sheet Revision History ... 87 The Microchip Web Site .. 88 Customer Change Notification Service ... 88 Customer Support ... 88 Product Identification System ... 89 2018 Microchip Technology Inc. DS00002776A-page 3 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service