Datasheet KSZ8462HLI, KSZ8462FHLI (Microchip) - 9
| Fabricante | Microchip |
| Descripción | IEEE 1588 Precision Time Protocol-Enabled, Two-Port, 10/100 Mbps Ethernet Switch with 8-or 16-Bit Host Interface |
| Páginas / Página | 233 / 9 — KSZ8462HLI/FHLI. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. … |
| Formato / tamaño de archivo | PDF / 2.4 Mb |
| Idioma del documento | Inglés |
KSZ8462HLI/FHLI. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 64-PIN LQFP ASSIGNMENT, (TOP VIEW). KSZ8462HL/KSZ8462FHL
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KSZ8462HLI/FHLI 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 64-PIN LQFP ASSIGNMENT, (TOP VIEW)
FXSD1 RSTN P2LED0/LEBE P2LED1 P1LED0/H816 P1LED1 GPIO6 DGND VDD_IO GPIO5/EECS GPIO4/EEDIO GPIO3/EESK GPIO2 VDD_L DGND GPIO1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 1 48 GPIO0 RXP1 2 47 CSN AGND 3 46 PME/EEPROM TXM1 4 45 WRN TXP1 5 44 RDN VDD_AL 6 43 INTRN
KSZ8462HL/KSZ8462FHL
ISET 7 42 CMD
(TOP VIEW)
AGND 8 41 SD0 VDD_A3.3 9 40 VDD_L RXM2 10 39 DGND RXP2 11 38 SD1 AGND 12 37 SD2 13 36 TXM2 SD3 14 35 TXP2 SD4 34 FXSD2 15 SD5 33 VDD_COL 16 SD6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 X1 X2 SD9 SD8 SD7 SD15 SD14 SD13 SD12 SD1 SD10 DGNG DGND PWRDN VDD_IO VDD_IO 2018 Microchip Technology Inc. DS00002641A-page 9 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 Media Access Controller (MAC) Block 3.4 Switch Block 3.5 Queue Management Unit (QMU) 3.6 IEEE 1588 Precision Time Protocol (PTP) Block 3.7 General Purpose and IEEE 1588 Input/Output (GPIO) 3.8 Using the GPIO Pins with the Trigger Output Units 3.9 Using the GPIO Pins with the Time Stamp Input Units 3.10 Device Clocks 3.11 Power 3.12 Power Management 3.13 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 Management Information Base (MIB) Counters 4.4 Static MAC Address Table 4.5 Dynamic MAC Address Table 4.6 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read/Write Timing 7.2 Auto-Negotiation Timing 7.3 Trigger Output Unit and Time Stamp Input Unit Timing 7.4 Serial EEPROM Interface Timing 7.5 Reset and Power Sequence Timing 7.6 Reset Circuit Guidelines 8.0 Reference Circuit: LED Strap-In Pins 9.0 Reference Clock: Connection and Selection 10.0 Selection of Isolation Transformers 11.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
FXSD1 RSTN P2LED0/LEBE P2LED1 P1LED0/H816 P1LED1 GPIO6 DGND VDD_IO GPIO5/EECS GPIO4/EEDIO GPIO3/EESK GPIO2 VDD_L DGND GPIO1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 1 48 GPIO0 RXP1 2 47 CSN AGND 3 46 PME/EEPROM TXM1 4 45 WRN TXP1 5 44 RDN VDD_AL 6 43 INTRN
KSZ8462HL/KSZ8462FHL
ISET 7 42 CMD
(TOP VIEW)
AGND 8 41 SD0 VDD_A3.3 9 40 VDD_L RXM2 10 39 DGND RXP2 11 38 SD1 AGND 12 37 SD2 13 36 TXM2 SD3 14 35 TXP2 SD4 34 FXSD2 15 SD5 33 VDD_COL 16 SD6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 X1 X2 SD9 SD8 SD7 SD15 SD14 SD13 SD12 SD1 SD10 DGNG DGND PWRDN VDD_IO VDD_IO 2018 Microchip Technology Inc. DS00002641A-page 9 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 Media Access Controller (MAC) Block 3.4 Switch Block 3.5 Queue Management Unit (QMU) 3.6 IEEE 1588 Precision Time Protocol (PTP) Block 3.7 General Purpose and IEEE 1588 Input/Output (GPIO) 3.8 Using the GPIO Pins with the Trigger Output Units 3.9 Using the GPIO Pins with the Time Stamp Input Units 3.10 Device Clocks 3.11 Power 3.12 Power Management 3.13 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 Management Information Base (MIB) Counters 4.4 Static MAC Address Table 4.5 Dynamic MAC Address Table 4.6 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read/Write Timing 7.2 Auto-Negotiation Timing 7.3 Trigger Output Unit and Time Stamp Input Unit Timing 7.4 Serial EEPROM Interface Timing 7.5 Reset and Power Sequence Timing 7.6 Reset Circuit Guidelines 8.0 Reference Circuit: LED Strap-In Pins 9.0 Reference Clock: Connection and Selection 10.0 Selection of Isolation Transformers 11.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service