Datasheet KSZ8462HLI, KSZ8462FHLI (Microchip)

KSZ8462HLI/FHLI IEEE 1588 Precision Time Protocol-Enabled, Two-Port, 10/100 Mbps Ethernet Switch with 8- or 16-Bit Host Interface Features Advanced Switch Capabilities
• Non-Blocking Store-and-Forward Switch Fabric
Management Capabilities
Ensures Fast Packet Delivery by Utilizing 1024 • The KSZ8462 Includes All the Functions of a 10/ Entry Forwarding Table 100BASE-T/TX/FX Switch System that Combines • IEEE 802.1Q VLAN for Up to 16 Groups with Full a Switch Engine, Frame Buffer Management, Range of VLAN IDs Address Look-Up Table, Queue Management, MIB Counters, Media Access Controllers (MAC) • IEEE 802.1p/Q Tag Insertion or Removal on a per and PHY Transceivers Port Basis (Egress) and Support Double-Tagging • Non-Blocking Store-and-Forward Switch Fabric • VLAN ID Tag/Untag Options on per Port Basis Ensures Fast Packet Delivery by Utilizing 1024 • Fully Compliant with IEEE 802.3/802.3u Stan- Entry Forwarding Table dards • Port Mirroring/Monitoring/Sniffing: Ingress and/or • IEEE 802.3x Full-Duplex with Force-Mode Option Egress Traffic to any Port and Half-Duplex Backpressure Collision Flow • MIB Counters for Fully Compliant Statistics Gath- Control ering: 34 Counters per Port • IEEE 802.1w Rapid Spanning Tree Protocol Sup- • Loopback Modes for Remote Failure Diagnostics port • Rapid Spanning Tree Protocol Support (RSTP) for • IGMP v1/v2/v3 Snooping for Multicast Packet Fil- Topology Management and Ring/Linear Recovery tering • QoS/CoS Packets Prioritization Support: 802.1p,
Robust PHY Ports
DiffServ-Based and Re-Mapping of 802.1p Prior- • Two Integrated IEEE 802.3/802.3u-Compliant ity Field per Port Basis on Four Priority Levels Ethernet Transceivers Supporting 10BASE-T and
IPv4/IPv6 QoS Support
100BASE-TX • Copper and 100BASE-FX Fiber Mode Support in • IPv6 Multicast Listener Discovery (MLD) Snoop- the KSZ8462FHL ing Support • Copper Mode Support in the KSZ8462HL • Programmable Rate Limiting at the Ingress and Egress Ports • On-Chip Termination Resistors and Internal Bias- ing for Differential Pairs to Reduce Power • Broadcast Storm Protection • HP Auto MDI/MDI-X Crossover Support Elimi- • 1K Entry Forwarding Table with 32K Frame Buffer nates the Need to Differentiate Between Straight • Four Priority Queues with Dynamic Packet Map- or Crossover Cables in Applications ping for IEEE 802.1p, IPv4 TOS (DIFFSERV), IPv6 Traffic Class, etc.
MAC Ports Comprehensive Configuration Registers Access
• Three Internal Media Access Control (MAC) Units • 2Kbyte Jumbo Packet Support • Complete Register Access via the Parallel Host Interface • Tail Tagging Mode (One byte Added before FCS) Support at Port 3 to Inform The Processor Which • Facility to Load MAC Address from EEPROM at Ingress Port Receives the Packet and its Priority Power-Up and Reset Time • Programmable MAC Addresses for Port 1 and • I/O Pin Strapping Facility to Set Certain Register Port 2 and Source Address Filtering for Imple- Bits from I/O Pins at Reset Time menting Ring Topologies • Control Registers Configurable On-the-Fly • MAC Filtering Function to Filter or Forward
IEEE 1588v2 PTP and Clock Synchronization
Unknown Unicast Packets • Fully Compliant with the IEEE 1588v2 Precision • Port 1 and Port 2 MACs Programmable as Either Time Protocol E2E or P2P Transparent Clock (TC) Ports for • One-Step or Two-Step Transparent Clock (TC) 1588 Support Timing Corrections • E2E (End-to-End) or P2P (Peer-to-Peer) Trans- parent Clock (TC)  2018 Microchip Technology Inc. DS00002641A-page 1 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 Media Access Controller (MAC) Block 3.4 Switch Block 3.5 Queue Management Unit (QMU) 3.6 IEEE 1588 Precision Time Protocol (PTP) Block 3.7 General Purpose and IEEE 1588 Input/Output (GPIO) 3.8 Using the GPIO Pins with the Trigger Output Units 3.9 Using the GPIO Pins with the Time Stamp Input Units 3.10 Device Clocks 3.11 Power 3.12 Power Management 3.13 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 Management Information Base (MIB) Counters 4.4 Static MAC Address Table 4.5 Dynamic MAC Address Table 4.6 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read/Write Timing 7.2 Auto-Negotiation Timing 7.3 Trigger Output Unit and Time Stamp Input Unit Timing 7.4 Serial EEPROM Interface Timing 7.5 Reset and Power Sequence Timing 7.6 Reset Circuit Guidelines 8.0 Reference Circuit: LED Strap-In Pins 9.0 Reference Clock: Connection and Selection 10.0 Selection of Isolation Transformers 11.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service