Datasheet ADA4254 (Analog Devices) - 10

ADA4254 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V V H L _ _ H H T T D S –OUT 1 24 +OUT C S D U U D S N S D O O V V D V V I I A A VOCM 2 23 GPIO0 8 7 6 5 4 3 2 2 2 2 2 2 2 2 AVSS 3 22 GPIO1 AVDD 4 21 GPIO2 +IN1 1 21 VOCM IOUT_LV 5 20 GPIO3 –IN1 2 20 –OUT ADA4254 +IN2 3 19 +OUT IOUT_HV 6 19 GPIO4 TOP VIEW –IN2 4 ADA4254 18 GPIO0 VDDH 7 18 CS DNC 5 TOP VIEW 17 GPIO1 VSSH 17 SCLK EPAD 8 DVSS 6 16 GPIO2 +IN1 9 16 SDI DVDD 7 15 GPIO3 –IN1 10 15 SDO 8 9 0 1 1 1 21 31 41 +IN2 11 14 DVDD O I K S 6 5 4
007
D D L C O –IN2 12 13 DVSS I OI OI
41-
S S C S P P P G G G
157
NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
006
2. CONNECT THE EXPOSED PAD (EPAD) TO VSSH.
15741- Figure 5. 28-Lead LFCSP Pin Configuration Figure 6. 24-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions Mnemonic LFCSP Pin No. TSSOP Pin No. Description
+IN1 1 9 Channel 1 Positive Input. −IN1 2 10 Channel 1 Negative Input. +IN2 3 11 Channel 2 Positive Input. −IN2 4 12 Channel 2 Negative Input. DNC 5, 28 Not applicable Do Not Connect. Do not connect to this pin. DVSS 6 13 Negative Digital Supply Voltage. DVDD 7 14 Positive Digital Supply Voltage. SDO 8 15 SPI Serial Data Output. SDI 9 16 SPI Serial Data Input. SCLK 10 17 SPI Serial Clock Input. CS 11 18 SPI Chip Select Input. GPIO6 12 Not applicable GPIO6/SCS6. GPIO5 13 Not applicable GPIO5/SCS5. GPIO4 14 19 GPIO4/SCS4/Clock Input or Output. GPIO3 15 20 GPIO3/SCS3/Fault Interrupt Output. GPIO2 16 21 GPIO2/SCS2/Calibration Busy Out. GPIO1 17 22 GPIO1/SCS1/External Multiplexer Control 1. GPIO0 18 23 GPIO0/SCS0/External Multiplexer Control 0. +OUT 19 24 Positive Output. −OUT 20 1 Negative Output. VOCM 21 2 Output Amplifier Common-Mode Voltage Input. This pin is high impedance and is not internally biased. AVSS 22 3 Output Amplifier Negative Supply Voltage. AVDD 23 4 Output Amplifier Positive Supply Voltage. IOUT_LV 24 5 Low Voltage Excitation Current Source Output. IOUT_HV 25 6 High Voltage Excitation Current Source Output. VDDH 26 7 Positive High Voltage Supply. VSSH 27 8 Negative High Voltage Supply. EPAD Not applicable Exposed Pad. Connect the exposed pad (EPAD) to VSSH. Rev. A | Page 10 of 59 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER INPUT MULTIPLEXER EMI REDUCTION AND INTERNAL EMI FILTER INPUT AMPLIFIER OUTPUT AMPLIFIER POWER SUPPLIES ESD MAP OUTPUT RIPPLE CALIBRATION CONFIGURATION GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs) EXCITATION CURRENTS EXTERNAL CLOCK SYNCHRONIZATION SEQUENTIAL CHIP SELECT (SCS) GAIN ERROR CALIBRATION WIRE BREAK DETECTION TEST MULTIPLEXER EXTERNAL MUX CONTROL DIGITAL INTERFACE SPI INTERFACE ACCESSING THE ADA4254 REGISTER MAP CHECKSUM PROTECTION CRC CALCULATION MEMORY MAP CHECKSUM PROTECTION READ-ONLY MEMORY (ROM) CHECKSUM PROTECTION SPI READ/WRITE ERROR DETECTION SPI COMMAND LENGTH ERROR DETECTION APPLICATIONS INFORMATION INPUT AND OUTPUT OFFSET VOLTAGE AND NOISE ADC CLOCK SYNCHRONIZATION PROGRAMMABLE LOGIC CONTROLLER (PLC)VOLTAGE/CURRENT INPUT 3-WIRE RTD WITH CURRENT EXCITATION HIGH RAIL CURRENT SENSING REGISTER SUMMARY REGISTER DETAILS GAIN_MUX REGISTER DETAILS Bit 7, G4—Output Amplifier Scaling Gain (1.375 V/V) Bits[6:3], G[3:0]—Input Amplifier Gain Setting Bits[1:0], EXT_MUX[1:0]—External Multiplexer Control SOFTWARE RESET REGISTER (RESET) DETAILS Bit 0, RST—Soft Reset CLOCK SYNCHRONIZATION CONFIGURATION REGISTER (SYNC_CFG) DETAILS Bit 6, CLK_OUT_SEL—Clock Output Select Bit 4, SYNC_POL—Clock Synchronization Polarity Bits[2:0], SYNC[2:0]—Internal Clock Divider Value DIGITAL ERROR REGISTER (DIGITAL_ERR) DETAILS Bit 6, CAL_BUSY—Calibration Busy (Read Only) Bit 5, SPI_CRC_ERR—SPI CRC Error Bit 4, SPI_RW_ERR—SPI Read/Write Error Bit 3, SPI_SCLK_CNT_ERR—SPI SCLK Count Error Bit 1, MM_CRC_ERR—Memory Map CRC Error Bit 0, ROM_CRC_ERR—ROM CRC Error ANALOG ERROR REGISTER (ANALOG_ERR) DETAILS Bit 7, G_RST—Gain Reset Flag Bit 6, POR_HV—Power-On Reset HV Supply Bit 4, WB_ERR—Wire Break Detect Error Bit 3, FAULT_INT—Fault Interrupt Bit 2, OUTPUT_ERR—Output Amplifier Error Bit 1, INPUT_ERR—Input Amplifier Error Bit 0, MUX_OVER_VOLT_ERR—Input Multiplexer Overvoltage Error GPIO DATA REGISTER (GPIO_DATA) DETAILS Bits[6:0], GPIO_DATA[6:0]—GPIO Data Values INTERNAL MUX CONTROL REGISTER (INPUT_MUX) DETAILS Bit 6, SW_A1, and Bit 5, SW_A2—Channel 1 Input Switches Bit 4, SW_B1, and Bit 3, SW_B2—Channel 2 Input Switches Bit 2, SW_C1, and Bit 1, SW_C2—PGIA Input Test Multiplexer Switches Bit 0, SW_D12—PGIA Input Short Switch WIRE BREAK DETECT REGISTER (WB_DETECT) DETAILS Bit 7, WB_G_RST_DIS—Wire Break Gain Reset Disable Bit 3, SW_F1, and Bit 2, SW_F2—Fault Switch Selection Bits[1:0], WB_CURRENT—Detection Current Selection GPIO DIRECTION REGISTER (GPIO_DIR) DETAILS Bits[6:0], GPIO_DIR—GPIO Direction Configuration SEQUENTIAL CHIP SELECT REGISTER (SCS) DETAILS Bits[6:0], SCS—Sequential Chip Select Configuration ANALOG ERROR MASK REGISTER (ANALOG_ERR_DIS) DETAILS Bit 7, G_RST_DIS—Disable Gain Reset Error Flag Bit 6, POR_HV_DIS—Disable High Voltage Power Reset Flag Bit 4, WB_ERR_DIS—Disable Wire-Break Detection Flag Bit 3, MUX_PROT_DIS—Disable Input Multiplexer Protection Bit 2, OUTPUT_ERR_DIS—Disable Output Amplifier Error Flag Bit 1, INPUT_ERR_DIS—Disable Input Amplifier Error Flag Bit 0, MUX_OVER_VOLT_ERR_DIS—Disable Multiplexer Overvoltage Flag. DIGITAL ERROR MASK REGISTER (DIGITAL_ERR_DIS) DETAILS Bit 6, CAL_BUSY_DIS—Disable Calibration Busy Error Flag Bit 5, SPI_CRC_ERR_DIS—Disable SPI CRC Error Flag Bit 4, SPI_RW_ERR_DIS—Disable SPI Read/Write Error Flag Bit 3, SPI_SCLK_CNT_ERR_DIS—Disable SPI SCLK Count Error Flag Bit 2, M_CLK_CNT_ERR_DIS—Disable Master Clock Count Output Bit 1, MM_CRC_ERR_DIS—Disable Memory Map CRC Error Flag Bit 0, ROM_CRC_ERR_DIS—Disable ROM CRC Error Flag SPECIAL FUNCTION CONFIGURATION REGISTER (SF_CFG) DETAILS Bit 5, INT_CLK_OUT—Internal Oscillator Output Bit 4, EXT_CLK_IN—External Oscillator Input Bit 3, FAULT_INT_OUT—Fault Interrupt Output Bit 2, CAL_BUSY_OUT—Calibration Busy Output Bits[1:0], EXT_MUX_EN[1:0]—Enable External Multiplexer Control ERROR CONFIGURATION REGISTER Bit 7, ERR_LATCH_DIS—Disable Error Latching Bits[3:0], ERR_DELAY[3:0] —Error Suppression Time TEST MULTIPLEXER REGISTER (TEST_MUX) DETAILS Bit 7, G5—Output Amplifier Scaling Gain = 1.25 V/V Bit 6, CAL_SEL—Calibration Type Configuration Bits[5:4], CAL_EN[1:0]—Scheduled Calibration Enable and Interval Bits[3:0], TEST_MUX[3:0]—Input Test Multiplexer Configuration EXCITATION CURRENT CONFIGURATION REGISTER (EX_CURRENT_CFG) DETAILS Bits[7:6], EX_CURRENT_SEL[1:0]—Excitation Current Connection Configuration Bits[3:0], EX_CURRENT[3:0]—Excitation Current Value GAIN CALIBRATION REGISTERS (GAIN_CALx) DETAILS TRIGGER CALIBRATION REGISTER (TRIG_CAL) DETAILS Bit 0, TRIG_CAL—Trigger Calibration Input MASTER CLOCK COUNT REGISTER (M_CLK_CNT) DETAILS Bits[7:0], M_CLK_CNT[7:0]—Master Clock Count DIE REVISION IDENTIFICATION REGISTER (DIE_REV_ID) DETAILS Bits[7:0], DIE_REV_ID[7:0]—Die Revision Identification Number DEVICE IDENTIFICATION REGISTERS (PART_ID) DETAILS PART_ID[39:0]—Part ID Number OUTLINE DIMENSIONS ORDERING GUIDE