Datasheet ADA4254 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier |
| Páginas / Página | 59 / 2 — ADA4254. Data Sheet. TABLE OF CONTENTS |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
ADA4254. Data Sheet. TABLE OF CONTENTS
Versión de texto del documento
link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 2 link to page 4 link to page 7 link to page 9 link to page 9 link to page 9 link to page 10 link to page 11 link to page 23 link to page 23 link to page 24 link to page 24 link to page 25 link to page 25 link to page 25 link to page 26 link to page 26 link to page 27 link to page 27 link to page 28 link to page 28 link to page 29 link to page 31 link to page 31 link to page 32 link to page 33 link to page 33 link to page 33 link to page 33 link to page 34 link to page 35 link to page 35 link to page 35 link to page 35 link to page 36 link to page 36 link to page 36 link to page 37 link to page 37 link to page 38 link to page 39 link to page 40 link to page 42 link to page 42 link to page 42 link to page 43 link to page 43 link to page 45 link to page 45 link to page 46 link to page 47 link to page 48 link to page 49 link to page 50 link to page 50 link to page 51 link to page 53 link to page 53 link to page 54 link to page 56 link to page 56 link to page 56 link to page 57 link to page 58 link to page 58 link to page 58 link to page 58 link to page 59 link to page 59
ADA4254 Data Sheet TABLE OF CONTENTS
Features .. 1 SPI Read/Write Error Detection .. 35 Applications ... 1 SPI Command Length Error Detection .. 35 General Description ... 1 Applications Information .. 36 Simplified Functional Block Diagram ... 1 Input and Output Offset Voltage and Noise ... 36 Companion Products ... 1 ADC Clock Synchronization .. 36 Revision History ... 3 Programmable Logic Control er (PLC) Voltage/Current Input Specifications ... 4 ... 37 Timing Specifications .. 8 3-Wire RTD With Current Excitation ... 38 Absolute Maximum Ratings .. 9 High Rail Current Sensing .. 39 Thermal Resistance .. 9 Register Summary .. 40 ESD Caution .. 9 Register Details ... 42 Pin Configurations and Function Descriptions ... 10 GAIN_MUX Register Details ... 42 Typical Performance Characteristics ... 11 Software Reset Register (Reset) Details ... 43 Theory of Operation .. 23 Clock Synchronization Configuration Register (SYNC_CFG) Details .. 44 Programmable Gain Instrumentation Amplifier ... 23 Digital Error Register (DIGITAL_ERR) Details .. 45 Input Multiplexer .. 24 Analog Error Register (ANALOG_ERR) Details .. 46 EMI Reduction and Internal EMI Filter .. 24 GPIO Data Register (GPIO_DATA) Details .. 47 Input Amplifier ... 25 Internal Mux Control Register (INPUT_MUX) Details... 48 Output Amplifier .. 25 Wire Break Detect Register (WB_DETECT) Details .. 49 Power Supplies .. 26 GPIO Direction Register (GPIO_DIR) Details .. 50 ESD Map .. 26 Sequential Chip Select Register (SCS) Details ... 50 Output Ripple Calibration Configuration .. 27 Analog Error Mask Register (ANALOG_ERR_DIS) Details .. 51 General-Purpose Inputs/Outputs (GPIOs)... 27 Digital Error Mask Register (DIGITAL_ERR_DIS) Details ... 52 Excitation Currents .. 28 Special Function Configuration Register (SF_CFG) Details ... 53 External Clock Synchronization ... 28 Error Configuration Register .. 54 Sequential Chip Select (SCS) .. 28 Test Multiplexer Register (TEST_MUX) Details ... 55 Gain Error Calibration... 30 Excitation Current Configuration Register Wire Break Detection .. 31 (EX_CURRENT_CFG) Details .. 56 Test Multiplexer .. 32 Gain Calibration Registers (GAIN_CALx) Details ... 57 External Mux Control .. 32 Trigger Calibration Register (TRIG_CAL) Details .. 58 Digital Interface .. 33 Master Clock Count Register (M_CLK_CNT) Details ... 58 SPI Interface .. 33 DIE Revision Identification Register (DIE_REV_ID) Details Accessing the ADA4254 Register Map .. 33 ... 58 Checksum Protection... 33 Device Identification Registers (PART_ID) Details .. 58 CRC Calculation ... 35 Outline Dimensions ... 59 Memory Map Checksum Protection ... 35 Ordering Guide .. 59 Read-Only Memory (ROM) Checksum Protection .. 35 Rev. A | Page 2 of 59 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER INPUT MULTIPLEXER EMI REDUCTION AND INTERNAL EMI FILTER INPUT AMPLIFIER OUTPUT AMPLIFIER POWER SUPPLIES ESD MAP OUTPUT RIPPLE CALIBRATION CONFIGURATION GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs) EXCITATION CURRENTS EXTERNAL CLOCK SYNCHRONIZATION SEQUENTIAL CHIP SELECT (SCS) GAIN ERROR CALIBRATION WIRE BREAK DETECTION TEST MULTIPLEXER EXTERNAL MUX CONTROL DIGITAL INTERFACE SPI INTERFACE ACCESSING THE ADA4254 REGISTER MAP CHECKSUM PROTECTION CRC CALCULATION MEMORY MAP CHECKSUM PROTECTION READ-ONLY MEMORY (ROM) CHECKSUM PROTECTION SPI READ/WRITE ERROR DETECTION SPI COMMAND LENGTH ERROR DETECTION APPLICATIONS INFORMATION INPUT AND OUTPUT OFFSET VOLTAGE AND NOISE ADC CLOCK SYNCHRONIZATION PROGRAMMABLE LOGIC CONTROLLER (PLC)VOLTAGE/CURRENT INPUT 3-WIRE RTD WITH CURRENT EXCITATION HIGH RAIL CURRENT SENSING REGISTER SUMMARY REGISTER DETAILS GAIN_MUX REGISTER DETAILS Bit 7, G4—Output Amplifier Scaling Gain (1.375 V/V) Bits[6:3], G[3:0]—Input Amplifier Gain Setting Bits[1:0], EXT_MUX[1:0]—External Multiplexer Control SOFTWARE RESET REGISTER (RESET) DETAILS Bit 0, RST—Soft Reset CLOCK SYNCHRONIZATION CONFIGURATION REGISTER (SYNC_CFG) DETAILS Bit 6, CLK_OUT_SEL—Clock Output Select Bit 4, SYNC_POL—Clock Synchronization Polarity Bits[2:0], SYNC[2:0]—Internal Clock Divider Value DIGITAL ERROR REGISTER (DIGITAL_ERR) DETAILS Bit 6, CAL_BUSY—Calibration Busy (Read Only) Bit 5, SPI_CRC_ERR—SPI CRC Error Bit 4, SPI_RW_ERR—SPI Read/Write Error Bit 3, SPI_SCLK_CNT_ERR—SPI SCLK Count Error Bit 1, MM_CRC_ERR—Memory Map CRC Error Bit 0, ROM_CRC_ERR—ROM CRC Error ANALOG ERROR REGISTER (ANALOG_ERR) DETAILS Bit 7, G_RST—Gain Reset Flag Bit 6, POR_HV—Power-On Reset HV Supply Bit 4, WB_ERR—Wire Break Detect Error Bit 3, FAULT_INT—Fault Interrupt Bit 2, OUTPUT_ERR—Output Amplifier Error Bit 1, INPUT_ERR—Input Amplifier Error Bit 0, MUX_OVER_VOLT_ERR—Input Multiplexer Overvoltage Error GPIO DATA REGISTER (GPIO_DATA) DETAILS Bits[6:0], GPIO_DATA[6:0]—GPIO Data Values INTERNAL MUX CONTROL REGISTER (INPUT_MUX) DETAILS Bit 6, SW_A1, and Bit 5, SW_A2—Channel 1 Input Switches Bit 4, SW_B1, and Bit 3, SW_B2—Channel 2 Input Switches Bit 2, SW_C1, and Bit 1, SW_C2—PGIA Input Test Multiplexer Switches Bit 0, SW_D12—PGIA Input Short Switch WIRE BREAK DETECT REGISTER (WB_DETECT) DETAILS Bit 7, WB_G_RST_DIS—Wire Break Gain Reset Disable Bit 3, SW_F1, and Bit 2, SW_F2—Fault Switch Selection Bits[1:0], WB_CURRENT—Detection Current Selection GPIO DIRECTION REGISTER (GPIO_DIR) DETAILS Bits[6:0], GPIO_DIR—GPIO Direction Configuration SEQUENTIAL CHIP SELECT REGISTER (SCS) DETAILS Bits[6:0], SCS—Sequential Chip Select Configuration ANALOG ERROR MASK REGISTER (ANALOG_ERR_DIS) DETAILS Bit 7, G_RST_DIS—Disable Gain Reset Error Flag Bit 6, POR_HV_DIS—Disable High Voltage Power Reset Flag Bit 4, WB_ERR_DIS—Disable Wire-Break Detection Flag Bit 3, MUX_PROT_DIS—Disable Input Multiplexer Protection Bit 2, OUTPUT_ERR_DIS—Disable Output Amplifier Error Flag Bit 1, INPUT_ERR_DIS—Disable Input Amplifier Error Flag Bit 0, MUX_OVER_VOLT_ERR_DIS—Disable Multiplexer Overvoltage Flag. DIGITAL ERROR MASK REGISTER (DIGITAL_ERR_DIS) DETAILS Bit 6, CAL_BUSY_DIS—Disable Calibration Busy Error Flag Bit 5, SPI_CRC_ERR_DIS—Disable SPI CRC Error Flag Bit 4, SPI_RW_ERR_DIS—Disable SPI Read/Write Error Flag Bit 3, SPI_SCLK_CNT_ERR_DIS—Disable SPI SCLK Count Error Flag Bit 2, M_CLK_CNT_ERR_DIS—Disable Master Clock Count Output Bit 1, MM_CRC_ERR_DIS—Disable Memory Map CRC Error Flag Bit 0, ROM_CRC_ERR_DIS—Disable ROM CRC Error Flag SPECIAL FUNCTION CONFIGURATION REGISTER (SF_CFG) DETAILS Bit 5, INT_CLK_OUT—Internal Oscillator Output Bit 4, EXT_CLK_IN—External Oscillator Input Bit 3, FAULT_INT_OUT—Fault Interrupt Output Bit 2, CAL_BUSY_OUT—Calibration Busy Output Bits[1:0], EXT_MUX_EN[1:0]—Enable External Multiplexer Control ERROR CONFIGURATION REGISTER Bit 7, ERR_LATCH_DIS—Disable Error Latching Bits[3:0], ERR_DELAY[3:0] —Error Suppression Time TEST MULTIPLEXER REGISTER (TEST_MUX) DETAILS Bit 7, G5—Output Amplifier Scaling Gain = 1.25 V/V Bit 6, CAL_SEL—Calibration Type Configuration Bits[5:4], CAL_EN[1:0]—Scheduled Calibration Enable and Interval Bits[3:0], TEST_MUX[3:0]—Input Test Multiplexer Configuration EXCITATION CURRENT CONFIGURATION REGISTER (EX_CURRENT_CFG) DETAILS Bits[7:6], EX_CURRENT_SEL[1:0]—Excitation Current Connection Configuration Bits[3:0], EX_CURRENT[3:0]—Excitation Current Value GAIN CALIBRATION REGISTERS (GAIN_CALx) DETAILS TRIGGER CALIBRATION REGISTER (TRIG_CAL) DETAILS Bit 0, TRIG_CAL—Trigger Calibration Input MASTER CLOCK COUNT REGISTER (M_CLK_CNT) DETAILS Bits[7:0], M_CLK_CNT[7:0]—Master Clock Count DIE REVISION IDENTIFICATION REGISTER (DIE_REV_ID) DETAILS Bits[7:0], DIE_REV_ID[7:0]—Die Revision Identification Number DEVICE IDENTIFICATION REGISTERS (PART_ID) DETAILS PART_ID[39:0]—Part ID Number OUTLINE DIMENSIONS ORDERING GUIDE
ADA4254 Data Sheet TABLE OF CONTENTS
Features .. 1 SPI Read/Write Error Detection .. 35 Applications ... 1 SPI Command Length Error Detection .. 35 General Description ... 1 Applications Information .. 36 Simplified Functional Block Diagram ... 1 Input and Output Offset Voltage and Noise ... 36 Companion Products ... 1 ADC Clock Synchronization .. 36 Revision History ... 3 Programmable Logic Control er (PLC) Voltage/Current Input Specifications ... 4 ... 37 Timing Specifications .. 8 3-Wire RTD With Current Excitation ... 38 Absolute Maximum Ratings .. 9 High Rail Current Sensing .. 39 Thermal Resistance .. 9 Register Summary .. 40 ESD Caution .. 9 Register Details ... 42 Pin Configurations and Function Descriptions ... 10 GAIN_MUX Register Details ... 42 Typical Performance Characteristics ... 11 Software Reset Register (Reset) Details ... 43 Theory of Operation .. 23 Clock Synchronization Configuration Register (SYNC_CFG) Details .. 44 Programmable Gain Instrumentation Amplifier ... 23 Digital Error Register (DIGITAL_ERR) Details .. 45 Input Multiplexer .. 24 Analog Error Register (ANALOG_ERR) Details .. 46 EMI Reduction and Internal EMI Filter .. 24 GPIO Data Register (GPIO_DATA) Details .. 47 Input Amplifier ... 25 Internal Mux Control Register (INPUT_MUX) Details... 48 Output Amplifier .. 25 Wire Break Detect Register (WB_DETECT) Details .. 49 Power Supplies .. 26 GPIO Direction Register (GPIO_DIR) Details .. 50 ESD Map .. 26 Sequential Chip Select Register (SCS) Details ... 50 Output Ripple Calibration Configuration .. 27 Analog Error Mask Register (ANALOG_ERR_DIS) Details .. 51 General-Purpose Inputs/Outputs (GPIOs)... 27 Digital Error Mask Register (DIGITAL_ERR_DIS) Details ... 52 Excitation Currents .. 28 Special Function Configuration Register (SF_CFG) Details ... 53 External Clock Synchronization ... 28 Error Configuration Register .. 54 Sequential Chip Select (SCS) .. 28 Test Multiplexer Register (TEST_MUX) Details ... 55 Gain Error Calibration... 30 Excitation Current Configuration Register Wire Break Detection .. 31 (EX_CURRENT_CFG) Details .. 56 Test Multiplexer .. 32 Gain Calibration Registers (GAIN_CALx) Details ... 57 External Mux Control .. 32 Trigger Calibration Register (TRIG_CAL) Details .. 58 Digital Interface .. 33 Master Clock Count Register (M_CLK_CNT) Details ... 58 SPI Interface .. 33 DIE Revision Identification Register (DIE_REV_ID) Details Accessing the ADA4254 Register Map .. 33 ... 58 Checksum Protection... 33 Device Identification Registers (PART_ID) Details .. 58 CRC Calculation ... 35 Outline Dimensions ... 59 Memory Map Checksum Protection ... 35 Ordering Guide .. 59 Read-Only Memory (ROM) Checksum Protection .. 35 Rev. A | Page 2 of 59 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER INPUT MULTIPLEXER EMI REDUCTION AND INTERNAL EMI FILTER INPUT AMPLIFIER OUTPUT AMPLIFIER POWER SUPPLIES ESD MAP OUTPUT RIPPLE CALIBRATION CONFIGURATION GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs) EXCITATION CURRENTS EXTERNAL CLOCK SYNCHRONIZATION SEQUENTIAL CHIP SELECT (SCS) GAIN ERROR CALIBRATION WIRE BREAK DETECTION TEST MULTIPLEXER EXTERNAL MUX CONTROL DIGITAL INTERFACE SPI INTERFACE ACCESSING THE ADA4254 REGISTER MAP CHECKSUM PROTECTION CRC CALCULATION MEMORY MAP CHECKSUM PROTECTION READ-ONLY MEMORY (ROM) CHECKSUM PROTECTION SPI READ/WRITE ERROR DETECTION SPI COMMAND LENGTH ERROR DETECTION APPLICATIONS INFORMATION INPUT AND OUTPUT OFFSET VOLTAGE AND NOISE ADC CLOCK SYNCHRONIZATION PROGRAMMABLE LOGIC CONTROLLER (PLC)VOLTAGE/CURRENT INPUT 3-WIRE RTD WITH CURRENT EXCITATION HIGH RAIL CURRENT SENSING REGISTER SUMMARY REGISTER DETAILS GAIN_MUX REGISTER DETAILS Bit 7, G4—Output Amplifier Scaling Gain (1.375 V/V) Bits[6:3], G[3:0]—Input Amplifier Gain Setting Bits[1:0], EXT_MUX[1:0]—External Multiplexer Control SOFTWARE RESET REGISTER (RESET) DETAILS Bit 0, RST—Soft Reset CLOCK SYNCHRONIZATION CONFIGURATION REGISTER (SYNC_CFG) DETAILS Bit 6, CLK_OUT_SEL—Clock Output Select Bit 4, SYNC_POL—Clock Synchronization Polarity Bits[2:0], SYNC[2:0]—Internal Clock Divider Value DIGITAL ERROR REGISTER (DIGITAL_ERR) DETAILS Bit 6, CAL_BUSY—Calibration Busy (Read Only) Bit 5, SPI_CRC_ERR—SPI CRC Error Bit 4, SPI_RW_ERR—SPI Read/Write Error Bit 3, SPI_SCLK_CNT_ERR—SPI SCLK Count Error Bit 1, MM_CRC_ERR—Memory Map CRC Error Bit 0, ROM_CRC_ERR—ROM CRC Error ANALOG ERROR REGISTER (ANALOG_ERR) DETAILS Bit 7, G_RST—Gain Reset Flag Bit 6, POR_HV—Power-On Reset HV Supply Bit 4, WB_ERR—Wire Break Detect Error Bit 3, FAULT_INT—Fault Interrupt Bit 2, OUTPUT_ERR—Output Amplifier Error Bit 1, INPUT_ERR—Input Amplifier Error Bit 0, MUX_OVER_VOLT_ERR—Input Multiplexer Overvoltage Error GPIO DATA REGISTER (GPIO_DATA) DETAILS Bits[6:0], GPIO_DATA[6:0]—GPIO Data Values INTERNAL MUX CONTROL REGISTER (INPUT_MUX) DETAILS Bit 6, SW_A1, and Bit 5, SW_A2—Channel 1 Input Switches Bit 4, SW_B1, and Bit 3, SW_B2—Channel 2 Input Switches Bit 2, SW_C1, and Bit 1, SW_C2—PGIA Input Test Multiplexer Switches Bit 0, SW_D12—PGIA Input Short Switch WIRE BREAK DETECT REGISTER (WB_DETECT) DETAILS Bit 7, WB_G_RST_DIS—Wire Break Gain Reset Disable Bit 3, SW_F1, and Bit 2, SW_F2—Fault Switch Selection Bits[1:0], WB_CURRENT—Detection Current Selection GPIO DIRECTION REGISTER (GPIO_DIR) DETAILS Bits[6:0], GPIO_DIR—GPIO Direction Configuration SEQUENTIAL CHIP SELECT REGISTER (SCS) DETAILS Bits[6:0], SCS—Sequential Chip Select Configuration ANALOG ERROR MASK REGISTER (ANALOG_ERR_DIS) DETAILS Bit 7, G_RST_DIS—Disable Gain Reset Error Flag Bit 6, POR_HV_DIS—Disable High Voltage Power Reset Flag Bit 4, WB_ERR_DIS—Disable Wire-Break Detection Flag Bit 3, MUX_PROT_DIS—Disable Input Multiplexer Protection Bit 2, OUTPUT_ERR_DIS—Disable Output Amplifier Error Flag Bit 1, INPUT_ERR_DIS—Disable Input Amplifier Error Flag Bit 0, MUX_OVER_VOLT_ERR_DIS—Disable Multiplexer Overvoltage Flag. DIGITAL ERROR MASK REGISTER (DIGITAL_ERR_DIS) DETAILS Bit 6, CAL_BUSY_DIS—Disable Calibration Busy Error Flag Bit 5, SPI_CRC_ERR_DIS—Disable SPI CRC Error Flag Bit 4, SPI_RW_ERR_DIS—Disable SPI Read/Write Error Flag Bit 3, SPI_SCLK_CNT_ERR_DIS—Disable SPI SCLK Count Error Flag Bit 2, M_CLK_CNT_ERR_DIS—Disable Master Clock Count Output Bit 1, MM_CRC_ERR_DIS—Disable Memory Map CRC Error Flag Bit 0, ROM_CRC_ERR_DIS—Disable ROM CRC Error Flag SPECIAL FUNCTION CONFIGURATION REGISTER (SF_CFG) DETAILS Bit 5, INT_CLK_OUT—Internal Oscillator Output Bit 4, EXT_CLK_IN—External Oscillator Input Bit 3, FAULT_INT_OUT—Fault Interrupt Output Bit 2, CAL_BUSY_OUT—Calibration Busy Output Bits[1:0], EXT_MUX_EN[1:0]—Enable External Multiplexer Control ERROR CONFIGURATION REGISTER Bit 7, ERR_LATCH_DIS—Disable Error Latching Bits[3:0], ERR_DELAY[3:0] —Error Suppression Time TEST MULTIPLEXER REGISTER (TEST_MUX) DETAILS Bit 7, G5—Output Amplifier Scaling Gain = 1.25 V/V Bit 6, CAL_SEL—Calibration Type Configuration Bits[5:4], CAL_EN[1:0]—Scheduled Calibration Enable and Interval Bits[3:0], TEST_MUX[3:0]—Input Test Multiplexer Configuration EXCITATION CURRENT CONFIGURATION REGISTER (EX_CURRENT_CFG) DETAILS Bits[7:6], EX_CURRENT_SEL[1:0]—Excitation Current Connection Configuration Bits[3:0], EX_CURRENT[3:0]—Excitation Current Value GAIN CALIBRATION REGISTERS (GAIN_CALx) DETAILS TRIGGER CALIBRATION REGISTER (TRIG_CAL) DETAILS Bit 0, TRIG_CAL—Trigger Calibration Input MASTER CLOCK COUNT REGISTER (M_CLK_CNT) DETAILS Bits[7:0], M_CLK_CNT[7:0]—Master Clock Count DIE REVISION IDENTIFICATION REGISTER (DIE_REV_ID) DETAILS Bits[7:0], DIE_REV_ID[7:0]—Die Revision Identification Number DEVICE IDENTIFICATION REGISTERS (PART_ID) DETAILS PART_ID[39:0]—Part ID Number OUTLINE DIMENSIONS ORDERING GUIDE