Datasheet PI6CG33401 (Diodes) - 3

A product Line of Diodes Incorporated
PI6CG33401 Pin Description Cont. Pin # Pin Name Type Description
17 OE1# Input CMOS Active low input for enabling Q1 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 18 Q1+ Output HCSL Differential true clock output 19 Q1- Output HCSL Differential complementary clock output 20 GNDA Power — Ground for analog circuitry 21 VDDA Power — Power supply for analog circuitry 22 Q2+ Output HCSL Differential true clock output 23 Q2- Output HCSL Differential complementary clock output 24 OE2# Input CMOS Active low input for enabling Q2 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 27 Q3+ Output HCSL Differential true clock output 28 Q3- Output HCSL Differential complementary clock output 29 OE3# Input CMOS Active low input for enabling Q3 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs Input notifies device to sample latched inputs and start up on first high 31 PD# Input CMOS assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pullup resistor. Latched select input to select spread-spectrum amount at initial power up. 32 SS_SEL_TRI Input Tri-level 1 = 0.5% spread, M = -0.25%, 0 = Spread off. This pin has an internal pulldown. Epad GND Power — Connect to ground PI6CG33401 Document Number DS41072 Rev 4-2 3 www.diodes.com September 2019 Diodes Incorporated