Datasheet PI6CG33401 (Diodes) - 2
| Fabricante | Diodes |
| Descripción | 3.3V Very-Low-Power 4-Output PCIe Clock Generator With On-Chip Termination |
| Páginas / Página | 23 / 2 — PI6CG33401. Pin Configuration. GND. Pin Description. Pin #. Pin Name. … |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
PI6CG33401. Pin Configuration. GND. Pin Description. Pin #. Pin Name. Type. Description
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A product Line of Diodes Incorporated
PI6CG33401 Pin Configuration
O SS_SEL_TRI PD# GND OE3# Q3- Q3+ GND V DD 32 31 30 29 28 27 26 25 GND 1 24 OE2# XTAL_IN/CLK 2 23 Q2- XTAL_OUT 3 22 Q2+ VDD_OSC 4 21 VDDA V
GND
DD_REFOUT 5 20 GNDA SADR/REFOUT 6 19 Q1- GND_REF 7 18 Q1+ GND_DIG 8 17 OE1# 9 10 11 12 13 14 15 16 O ATA Q0+ Q0- _DIG SCLK D OE0# GND V DD S V DD
Pin Description Pin # Pin Name Type Description
1, 15, 26, 30 GND Power — Ground pin 2 XTAL_IN/CLK Input — Crystal input or CMOS reference input 3 XTAL_OUT Output — Crystal output 4 VDD_OSC Power — Power supply for oscillator circuitry, nominal 3.3V 5 VDD_REFOUT Power — Power supply for buffered CMOS output 6 SADR/REFOUT Input/ Output CMOS Latch to select SMBus Address or LVCMOS REFOUT. This pin has an internal pulldown. 7 GND_REF Power — Ground for REFOUT 8 GND_DIG Power — Ground for digital circuitry 9 VDD_DIG Power — Power supply for digital circuitry, nominal 3.3V 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 11 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 12 OE0# Input CMOS Active low input for enabling Q0 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 16, 25 VDDO Power — Power supply for differential outputs PI6CG33401 Document Number DS41072 Rev 4-2 2 www.diodes.com September 2019 Diodes Incorporated
PI6CG33401 Pin Configuration
O SS_SEL_TRI PD# GND OE3# Q3- Q3+ GND V DD 32 31 30 29 28 27 26 25 GND 1 24 OE2# XTAL_IN/CLK 2 23 Q2- XTAL_OUT 3 22 Q2+ VDD_OSC 4 21 VDDA V
GND
DD_REFOUT 5 20 GNDA SADR/REFOUT 6 19 Q1- GND_REF 7 18 Q1+ GND_DIG 8 17 OE1# 9 10 11 12 13 14 15 16 O ATA Q0+ Q0- _DIG SCLK D OE0# GND V DD S V DD
Pin Description Pin # Pin Name Type Description
1, 15, 26, 30 GND Power — Ground pin 2 XTAL_IN/CLK Input — Crystal input or CMOS reference input 3 XTAL_OUT Output — Crystal output 4 VDD_OSC Power — Power supply for oscillator circuitry, nominal 3.3V 5 VDD_REFOUT Power — Power supply for buffered CMOS output 6 SADR/REFOUT Input/ Output CMOS Latch to select SMBus Address or LVCMOS REFOUT. This pin has an internal pulldown. 7 GND_REF Power — Ground for REFOUT 8 GND_DIG Power — Ground for digital circuitry 9 VDD_DIG Power — Power supply for digital circuitry, nominal 3.3V 10 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 11 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 12 OE0# Input CMOS Active low input for enabling Q0 pair. This pin has an internal pulldown. 1 =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 16, 25 VDDO Power — Power supply for differential outputs PI6CG33401 Document Number DS41072 Rev 4-2 2 www.diodes.com September 2019 Diodes Incorporated