Datasheet 48L256 (Microchip) - 7

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48L256 2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE Name 8-Lead SOIC Description
CS 1 Chip Select Input SO 2 Serial Data Output VCAP 3 External Capacitor VSS 4 Ground SI 5 Serial Data Input SCK 6 Serial Clock Input HOLD 7 Hold Input VCC 8 Supply Voltage
2.1 Chip Select (CS) 2.5 Hold (HOLD)
A low level on this pin selects the device. A high level The HOLD pin is used to suspend transmission to the deselects the device and forces it into Standby mode. 48L256 while in the middle of a serial sequence without When the device is deselected, SO goes to the having to retransmit the entire sequence over again. It high-impedance state, allowing multiple parts to share must be held high any time this function is not being the same SPI bus. A low-to-high transition on CS after used. Once the device is selected and a serial a valid write sequence completes the SRAM write sequence is underway, the HOLD pin may be pulled cycle. After power-up, a high-to-low transition on CS is low to pause further serial communication without required prior to any sequence being initiated. resetting the serial sequence. The HOLD pin should be brought low while SCK is low,
2.2 Serial Output (SO)
otherwise the Hold function will not be invoked until the next SCK high-to-low transition. The 48L256 must The SO pin is used to transfer data out of the 48L256. During a read cycle, data is shifted out on this pin after remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is the falling edge of the serial clock. paused and any transitions on these pins will be ignored. To resume serial communication, the HOLD
2.3 Serial Input (SI)
pin should be brought high while the SCK pin is low, The SI pin is used to transfer data into the device. It otherwise serial communication will not be resumed receives instructions, addresses, and data. Data is until the next SCK high-to-low transition. latched on the rising edge of the serial clock. The SO line wil tri-state immediately upon a high-to-low transition of the HOLD pin, and wil begin
2.4 Serial Clock (SCK)
outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of The SCK is used to synchronize the communication the state of SCK. between a master and the 48L256. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.  2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 7 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L256 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L256 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales and Service