Datasheet 48L256 (Microchip) - 10

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48L256 4.2 DEVICE OPCODES
The 48L256 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained 4.2.1 SERIAL OPCODE in Table 4-1. All instructions, addresses and data are transferred with the MSb first and are initiated with a After the device is selected by driving CS low, the first high-to-low CS transition and completed with a byte sent must be the opcode that defines the low-to-high CS transition. operation to be performed.
TABLE 4-1: INSTRUCTION SET FOR 48L256 Address Data Reference Command Operation Description Opcode Bytes Bytes Section Write Control Commands
WREN Set Write Enable Latch (WEL) 06h 0000 0110 0 0 5.1 WRDI Reset Write Enable Latch (WEL) 04h 0000 0100 0 0 5.2
SRAM Commands
WRITE Write to SRAM Array 02h 0000 0010 2 1+ 8.0 READ Read from SRAM Array 03h 0000 0011 2 1+ 7.1 RDLSWA Read Last Successfully Written Address 0Ah 0000 1010 0 2 7.2 Secure Secure Write to SRAM Array with CRC 12h 0001 0010 2 64 10.1 WRITE Secure Secure Read from SRAM Array with CRC 13h 0001 0011 2 64 10.2 READ
STATUS Register Commands
WRSR Write STATUS Register (SR) 01h 0000 0001 0 1 6.5 RDSR Read STATUS Register (SR) 05h 0000 0101 0 1 6.4
Store/Recall Commands
STORE Store SRAM data to EEPROM array 08h 0000 1000 0 0 11.3 RECALL Copy EEPROM data to SRAM array 09h 0000 1001 0 0 11.4
Nonvolatile User Space Commands
WRNUR Write Nonvolatile User Space C2h 1100 0010 0 2 9.1 RDNUR Read Nonvolatile User Space C3h 1100 0011 0 2 9.2
Hibernate Commands
Hibernate Enter Hibernate mode B9h 1011 1001 0 0 12.0 4.2.2 HOLD FUNCTION To end the Hold mode and resume serial communication, the HOLD pin must be deasserted The HOLD pin is used to pause the serial during the SCK low pulse. If the HOLD pin is communication with the device without having to stop deasserted during the SCK high pulse, then the Hold or reset the clock sequence. The Hold mode, however, mode will not end until the beginning of the next SCK does not have an effect on the internal write cycle. low pulse. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the operation and the write If the CS pin is deasserted while the HOLD pin is still cycle will continue until it is finished. asserted, then any operation that may have been started will be aborted and the device will reset the The Hold mode can only be entered while the CS pin is WEL bit in the STATUS register back to the logic ‘0’ asserted. The Hold mode is activated by asserting the state. HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode wil not be started until the beginning of the next SCK low pulse. The device wil remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in Hold mode, the SO pin will be in a high-imped- ance state. In addition, both the SI pin and the SCK pin will be ignored.  2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 10 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L256 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L256 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales and Service