Datasheet GW1NRF (GOWIN Semiconductor) - 7

link to page 50 link to page 52 link to page 55 link to page 56 link to page 57 link to page 57 link to page 57 link to page 58 link to page 58 link to page 60 link to page 60 link to page 78 link to page 78 link to page 78 link to page 79 link to page 80 link to page 80 link to page 81 link to page 82 link to page 84 link to page 84 link to page 85 List of Figures Figure 3-33 GW1NRF User Flash Ports .. 41 Figure 3-34 DSP Macro ... 43 Figure 3-35 GW1NRF-4B Clock Resources .. 46 Figure 3-36 GCLK Quadrant Distribution ... 47 Figure 3-37 DQCE Concept ... 48 Figure 3-38 DCS Concept .. 48 Figure 3-39 DCS Rising Edge .. 48 Figure 3-40 DCS Falling Edge ... 49 Figure 3-41 PLL Structure .. 49 Figure 3-42 GW1NRF HCLK Distribution .. 51 Figure 3-43 GW1NRF DLL Function .. 51 Figure 4-1 GW1NRF User Flash Read Operation ... 69 Figure 4-2 GW1NRF User Flash Program Operation ... 69 Figure 4-3 GW1NRF User Flash Erase Operation .. 69 Figure 4-4 JTAG Timing ... 70 Figure 4-5 Power Recycle Timing .. 71 Figure 4-6 RECONFIG_N Trigger Timing .. 71 Figure 4-7 SSPI Timing Diagram ... 72 Figure 4-8 MSPI Timing Diagram ... 73 Figure 5-1 Part Naming–ES ... 75 Figure 5-2 Part Naming–Production .. 75 Figure 5-3 Package Mark ... 76 DS891-1.0E iv Document Outline Disclaimer Revision History Contents List of Figures List of Tables 1 About This Guide 1.1 Purpose 1.2 Supported Products 1.3 Related Documents 1.4 Abbreviations and Terminology 1.5 Support and Feedback 2 General Description 2.1 Features 2.2 Product Resources 2.3 Package Information 3 Architecture 3.1 Architecture Overview 3.2 SoC System FPU Memories Security Peripherals 3.2.1 Bluetooth Module Bluetooth Controller Mode Bluetooth Companion Mode Bluetooth Application Mode 3.2.2 Timers 3.2.3 Power Management DC DC Switching Power Supply Supply Monitoring 3.2.4 RF Description 3.2.5 Operating Modes 3.2.6 Software Development 3.3 Configurable Function Unit 3.3.1 CLU Register 3.3.2 CRU 3.4 IOB 3.4.1 I/O Buffer 3.4.2 True LVDS Design 3.4.3 I/O Logic IODELAY I/O Register IEM De-serializer DES and Clock Domain Transfer Serializer SER 3.4.4 I/O Logic Modes Basic Mode SDR Mode Generic DDR Mode IDES4 OSER4 Mode IVideo Mode OVideo Mode IDES8 Mode OSER8 Mode IDES10 Mode OSER10 Mode 3.5 Block SRAM (B-SRAM) 3.5.1 Introduction 3.5.2 Configuration Mode 3.5.3 Mixed Data Bus Width Configuration 3.5.4 Byte-enable 3.5.5 Parity Bit 3.5.6 Synchronous operation 3.5.7 Power up Conditions 3.5.8 Operation Modes Single Port Mode Dual Port Mode Semi-Dual Port Mode Read Only 3.5.9 B-SRAM Operation Modes Read Mode Pipeline Mode Bypass Mode Write Mode 3.5.10 Clock Operations Independent Clock Mode Read/Write Clock Operation Single Port Clock Mode 3.6 User Flash 3.6.1 Introduction 3.6.2 User Flash Ports 3.6.3 User Flash Mode Truth Table User Modes 3.7 DSP 3.7.1 Introduction Macro PADD MULT ALU 3.7.2 DSP Operations 3.8 Clock 3.8.1 Global Clock 3.8.2 PLL 3.8.3 HCLK 3.8.4 DLL 3.9 Long Wire (LW) 3.10 Global Set/Reset (GSR) 3.11 Programming Configuration 3.11.1 SRAM Configuration 3.11.2 Flash Configuration 3.12 On Chip Oscillator 4 AC/DC Characteristics 4.1 Operating Conditions 4.2 ESD 4.3 DC Characteristics 4.3.1 Static Current 4.3.2 RF Parameters 4.3.3 I/O Characteristics 4.4 Switching Characteristics 4.4.1 Internal Switching Characteristics 4.4.2 External Switching Characteristics 4.5 User Flash Characteristics 4.5.1 DC Characteristics1 4.5.2 Timing Parameters1,5,6 4.5.3 Operation Timing Diagrams 4.6 Configuration Interface Timing Specification 4.6.1 JTAG Port Timing Specifications 4.6.2 AUTO BOOT Port Timing Specifications 4.6.3 SSPI Port Timing Specifications 4.6.4 MSPI Port Timing Specifications 4.6.5 DUAL BOOT 4.6.6 CPU 4.6.7 SERIAL 5 Ordering Information 5.1 Part Name 5.2 Package Mark