Datasheet AD8304 (Analog Devices) - 5

AD8304 10 10 10nA100nA1 A 10 A 9 0 100 A 1nA 10mA 8 –10 1mA 7 –20 6 –30 5 4 –40 AND NOISE – mV rms 3 –50 WIDEB NORMALIZED RESPONSE – dB 2 –60 1 –70 0 100 1k 10k 100k 1M 10M 100M 1n 10n 100n 1 10 100 1m 10m FREQUENCY – Hz INPUT CURRENT – A
TPC 7. Small Signal AC Response, I TPC 10. Total Wideband Noise Voltage at V PD to VLOG LOG vs. IPD (5% Sine Modulation of IPD at Frequency)
100 3 GAIN = 1 , 2 , 2.5 , 5 10kHz 100kHz 0 10 AV = 5 AV = 1 –3 Hz A 1 V = 2.5 V rms/ 100Hz –6 AV = 2 1kHz 1MHz 0.1 NORMALIZED RESPONSE – dB –9 0.01 –12 1n 10n 100n 1 10 100 1m 10m 100 1k 10k 100k 1M 10M 100M I FREQUENCY – Hz PD – A
TPC 8. Spot Noise Spectral Density at V TPC 11. Small Signal Response of Buffer LOG vs. IPD
100 10 fC = 1kHz 1nA 0 10 –10 10nA 1 A –20 Hz 100nA 1 –30 V rms/ 10 A –40 >100 A NORMALIZED GAIN – dB 0.1 –50 –60 0.01 –70 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k FREQUENCY – Hz FREQUENCY – Hz
TPC 9. Spot Noise Spectral Density at V TPC 12. Small Signal Response of Buffer LOG vs. Frequency Operating as Two-Pole Filter REV. A –5– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS ORDERING GUIDE Typical Performance Characteristics BASIC CONCEPTS Optical Measurements Decibel Scaling GENERAL STRUCTURE Bandwidth and Noise Considerations Chip Enable USING THE AD8304 Slope and Intercept Adjustments Low Supply Slope and Intercept Adjustment Using the Adaptive Bias Changing the Voltage at the Summing Node Implementing Low-Pass Filters Operation in Comparator Modes Using a Negative Supply APPLICATIONS Summing Node at Ground and Voltage Inputs Providing Negative Outputs and Rescaling Inverting the Slope Programmable Level Comparator with Hysteresis Programmable Multidecade Current Source Characterization Setups and Methods Evaluation Board OUTLINE DIMENSIONS Revision History