Datasheet AD8304 (Analog Devices)

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160 dB Range (100 pA –10 mA) Logarithmic Converter AD8304 FEATURES FUNCTIONAL BLOCK DIAGRAM Optimized for Fiber Optic Photodiode Interfacing Eight Full Decades of Range VPS2 PWDN VPS1 10 Law Conformance 0.1 dB from 1 nA to 1 mA 2 12 AD8304 Single-Supply Operation (3.0 V– 5.5 V) Complete and Temperature Stable PDB BIAS VREF 7 VREF VPDB Accurate Laser-Trimmed Scaling: 6 ~10k 0.5V Logarithmic Slope of 10 mV/dB (at VLOG Pin) VSUM 3 Basic Logarithmic Intercept at 100 pA IPD 8 INPT VLOG 4 Easy Adjustment of Slope and Intercept 9 5k BFIN Output Bandwidth of 10 MHz, 15 V/ s Slew Rate TEMPERATURE VSUM 5 COMPENSATION 1-, 2-, or 3-Pole Low-Pass Filtering at Output 13 BFNG Miniature 14-Lead Package (TSSOP) Low Power: ~4.5 mA Quiescent Current (Enabled) APPLICATIONS 1 14 11 High Accuracy Optical Power Measurement VNEG ACOM VOUT Wide Range Baseband Log Compression Versatile Detector for APC Loops PRODUCT DESCRIPTION
The default value of the logarithmic slope at the output VLOG is The AD8304 is a monolithic logarithmic detector optimized for accurately scaled to 10 mV/dB (200 mV/decade). The resistance the measurement of low frequency signal power in fiber optic at this output is laser-trimmed to 5 kΩ, allowing the slope to be systems. It uses an advanced translinear technique to provide an lowered by shunting it with an external resistance; the addition exceptionally large dynamic range in a versatile and easily used of a capacitor at this pin provides a simple low-pass filter. The form. Its wide measurement range and accuracy are achieved intermediate voltage VLOG is buffered in an output stage that can using proprietary design techniques and precise laser trimming. swing to within about 100 mV of ground (or VN) and the posi- In most applications only a single positive supply, VP, of 5 V tive supply, VP, and provides a peak current drive capacity of will be required, but 3.0 V to 5.5 V can be used, and certain ±20 mA. The slope can be increased using the buffer and a pair applications benefit from the added use of a negative supply, of external feedback resistors. An accurate voltage reference of VN. When using low supply voltages, the log slope is readily 2 V is also provided to facilitate the repositioning of the intercept. altered to fit the available span. The low quiescent current and Many operational modes are possible. For example, low-pass filters chip disable features facilitate use in battery-operated applications. of up to three poles may be implemented, to reduce the output The input current, IPD, flows in the collector of an optimally noise at low input currents. The buffer may also serve as a com- scaled NPN transistor, connected in a feedback path around a parator, with or without hysteresis, using the 2 V reference, for low offset JFET amplifier. The current-summing input node example, in alarm applications. The incremental bandwidth of operates at a constant voltage, independent of current, with a a translinear logarithmic amplifier inherently diminishes for small default value of 0.5 V; this may be adjusted over a wide range, input currents. At the 1 nA level, the AD8304’s bandwidth is including ground or below, using an optional negative supply. about 2 kHz, but this increases in proportion to IPD up to a An adaptive biasing scheme is provided for reducing the dark maximum value of 10 MHz. current at very low light input levels. The voltage at Pin VPDB The AD8304 is available in a 14-lead TSSOP package and specified applies approximately 0.1 V across the diode for IPD = 100 pA, for operation from –40°C to +85°C. rising linearly with current to 2.0 V of net bias at IPD = 10 mA. The input pin INPT is flanked by the guard pins VSUM that track the voltage at the summing node to minimize leakage. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
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Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS ORDERING GUIDE Typical Performance Characteristics BASIC CONCEPTS Optical Measurements Decibel Scaling GENERAL STRUCTURE Bandwidth and Noise Considerations Chip Enable USING THE AD8304 Slope and Intercept Adjustments Low Supply Slope and Intercept Adjustment Using the Adaptive Bias Changing the Voltage at the Summing Node Implementing Low-Pass Filters Operation in Comparator Modes Using a Negative Supply APPLICATIONS Summing Node at Ground and Voltage Inputs Providing Negative Outputs and Rescaling Inverting the Slope Programmable Level Comparator with Hysteresis Programmable Multidecade Current Source Characterization Setups and Methods Evaluation Board OUTLINE DIMENSIONS Revision History