Datasheet 5L2503 (IDT)

MicroClock Programmable Clock 5L2503 Generator Datasheet Description Features
The 5L2503 MicroClock programmable clock generator is ▪ Configurable OE1 pin function as OE, PPS or DFC control intended for low-power, consumer, wearable and smart devices. function The 5L2503 device is a 3 PLL architecture design. Each PLL is ▪ Proactive Power Saving (PPS) features save power during the individually programmable, al owing up to 3 unique frequency end device power down mode outputs. The 5L2503 has built-in unique features such as ▪ Dynamic Frequency Control (DFC) feature allows programming Proactive Power Saving (PPS) to deliver better system level up to 4 difference frequencies switch dynamically power management. ▪ Spread spectrum clock support to lower system EMI An internal OTP memory allows the user to store the configuration ▪ I2C Interface in the device without programming after power-up, and then can be reprogrammed again through the I2C interface.
Output Features
The device has programmable VCO and PLL source selection ▪ 3 LVCMOS outputs: 1MHz–125MHz allowing the user to do power-performance optimization based on ▪ Low Power 32.768kHz clock supported the application requirements. A low-power 32.768kHz clock is supported with only less than 2μA current consumption for system ▪ Wireless clock crystal integration and fan out directly RTC reference clock needs.
Key Specifications Typical Applications
▪ 2μA operation for RTC clock 32.768kHz output ▪ SmartDevice ▪ 2.5 × 2.5 mm 12-DFN smal form factor package ▪ Handheld ▪ Wearable applications ▪ Consumer application crystal replacements
Block Diagram
Power Monitor VDD1_8 OE1 POR VSS PLL1 OUT1 XOUT OSC CLKIN/ XIN Mux PLL2 OUT2 & Divider VDDO Calibration VSS PLL3 OUT3 32.768K DCO SEL_DFC/ SCL_DFC1/OE3 Overshoot Reduction I2C Engine Dynamic Frequency Control Logic (DFC) (ORT) SDA_DFC0/OE2 OTP memory (1 configuration ) Proactive Power Saving Logic (PPS) ©2017 Integrated Device Technology, Inc. 1 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History