Datasheet ADA8282 (Analog Devices) - 9 Fabricante Analog Devices Descripción Radar Receive Path AFE: 4-Channel LNA and PGA Páginas / Página 21 / 9 — Data Sheet. ADA8282. 200. NO LOAD 5pF. GAIN = 36dB. 33pF. 150. 66pF. … Formato / tamaño de archivo PDF / 517 Kb Idioma del documento Inglés
Data Sheet. ADA8282. 200. NO LOAD 5pF. GAIN = 36dB. 33pF. 150. 66pF. 100pF. GAIN = 30dB. ) s µ. 100. GAIN = 24dB. E (V/. UT O. GAIN = 18dB. EW SL. –50. 400
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Línea de modelo para esta hoja de datos Versión de texto del documento Data Sheet ADA8282 200 30 NO LOAD 5pF 29 GAIN = 36dB 33pF 150 66pF 28 100pF GAIN = 30dB 27 ) s µ 100 26 GAIN = 24dB V) E (V/ (m T 25 A UT O R GAIN = 18dB V 50 24 EW SL 23 0 22 21 –50 20 16 190 200 400 600 800 1000 1–40 –25 10 5 20 35 50 65 80 95 110 125 1TIME (ns) 13132-TEMPERATURE (°C) 13132- Figure 15. Pulse Response at Various Output Capacitive Loads Figure 18. Output Slew Rate vs. Temperature1.5 3.4 MODE 0 3.0 MODE 1 2.6 MODE 2 1.0 MODE 3 2.2 1.8 1.4 0.5 1.0 0.6 (V) (V) 0.2 0 UT UT O O –0.2 V V –0.6 –1.0 –0.5 –1.4 –1.8 –1.0 –2.2 –2.6 –3.0 –1.5 –3.4 0 100 200 300 400 500 600 700 800 900 1000 12118 24 30 36 125TIME (ns) 13132-GAIN (dB) 13132- Figure 16. Large Signal Pulse Response for Various LNA and PGA Bias Modes Figure 19. Maximum and Minimum Differential VOUT vs. Gain500 4 480 3 460 ) V mA) ( 2 G ( 440 NT WIN 1 420 S GE CURRE 400 T 0 OLTA 380 RCUI –1 T V -CI U 360 RT TP TA = +85°C –2 T HO A = +25°C 340 OU S TA = –40°C –3 320 300 –4 18–40 –25 10 5 20 35 50 65 80 95 110 125 1 1710 100 1k 10k 100k 1TEMPERATURE (°C) 13132-OUTPUT LOAD RESISTANCE (Ω) 13132- Figure 17. Short-Circuit Current vs. Temperature Per Channel Figure 20. Differential Output Voltage Swing vs. Output Load Resistance Rev. 0 | Page 9 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS