Datasheet ADA8282 (Analog Devices) - 3

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Data Sheet ADA8282 SPECIFICATIONS
AVDD = 3.3 V, LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = −40°C to +125°C, PGA_BIAS_SEL = b’10, LNA_BIAS_SEL= b’10, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ANALOG CHANNEL CHARACTERISTICS Gain 18/24/30/36 dB Gain Range 18 dB Gain Error ±0.5 dB −3 dB Bandwidth VOUT = 100 mV p-p, gain = 36 dB PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 5 20.5 MHz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 5 34.2 MHz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 5 42.3 MHz PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 5 52.3 MHz Channel to Channel Gain Matching Frequencies up to 5 MHz 0.1 ±0.25 dB Channel to Channel Phase Matching1 Frequencies up to 5 MHz 0.1 ±1 Degrees Slew Rate 28 V/μs Input Referred Noise Gain = 36 dB at 2 MHz PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 4.5 nV/√Hz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 3.8 nV/√Hz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 3.6 nV/√Hz PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 3.4 nV/√Hz 50 Ω impedance used for voltage to power −156 dBm/Hz conversion Output Referred Noise Gain = 18 dB 36 nV/√Hz Gain = 24 dB 61 nV/√Hz Gain = 30 dB 115 nV/√Hz Gain = 36 dB 218 nV/√Hz Offset Voltage Referred to Input Gain = 36 dB ±0.8 ±3 mV Referred to Output Gain = 36 dB ±50 ±200 mV SPI Offset Adjustment Resolution LNA_BIAS_SEL = b’00 113 μV (Relative to Input) LNA_BIAS_SEL = b’01 186 μV LNA_BIAS_SEL = b’10 250 μV LNA_BIAS_SEL = b’11 440 μV SPI Offset Adjustment Range (Relative LNA_BIAS_SEL = b’00 ±4 mV to Input) LNA_BIAS_SEL = b’01 ±6 mV LNA_BIAS_SEL = b’10 ±8 mV LNA_BIAS_SEL = b’11 ±14 mV Harmonic Distortion Second Harmonic (HD2) VOUT = 2 V p-p, fIN = 100 kHz −70 dBc VOUT = 100 mV p-p, fIN = 2 MHz −85 dBc Third Harmonic (HD3) VOUT = 2 V p-p, fIN = 100 kHz −85 dBc VOUT = 100 mV p-p, fIN = 2 MHz −95 dBc Intermodulation Distortion VOUT = 2 V p-p, fIN1 = 100 kHz, fIN2 = 150 kHz −72 dBc VOUT = 100 mV p-p, fIN1 = 2 MHz, fIN2 = 2.1 MHz −83 dBc Common-Mode Rejection Ratio (CMRR) −80 dB Crosstalk −105 dBc Rev. 0 | Page 3 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS