Datasheet AD9467-EP (Analog Devices) - 3

Enhanced Product AD9467-EP SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 1. Parameter1 Temp Min Typ Max Unit
RESOLUTION 16 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −200 0 +200 LSB Gain Error Full −3.9 −0.1 +2.6 %FSR Differential Nonlinearity (DNL)2 Full −0.9 ±0.5 +1.5 LSB Integral Nonlinearity (INL)2 Full −12 ±3.5 +12 LSB TEMPERATURE DRIFT Offset Error Full ±0.023 %FSR/°C Gain Error Full ±0.036 %FSR/°C ANALOG INPUTS Differential Input Voltage Range (Internal VREF = 1 V to 1.25 V) Full 2 2.5 2.5 V p-p Common-Mode Voltage 25°C 2.15 V Differential Input Resistance 25°C 530 Ω Differential Input Capacitance 25°C 3.5 pF Full Power Bandwidth 25°C 900 MHz XVREF INPUT Input Voltage Full 1 1.25 V Input Capacitance Full 3 pF POWER SUPPLY AVDD1 Full 1.75 1.8 1.85 V AVDD2 Full 3.0 3.3 3.6 V AVDD3 Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V IAVDD1 Full 567 620 mA IAVDD2 Full 55 61 mA IAVDD3 Full 31 35 mA IDRVDD Full 40 43 mA Total Power Dissipation (Including Output Drivers) Full 1.33 1.5 W Power-Down Dissipation Full 4.4 90 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Rev. 0 | Page 3 of 15 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE