Datasheet AD9253-EP (Analog Devices) - 8

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AD9253-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C C SE B DD DD AS N+ N–C EF DD I I V V CM V N–BI N+I V V A A SYN V VR SEN RBI A V V 48 47 46 45 44 43 42 41 40 39 38 37 VIN+D 1 36 VIN+A VIN–D 2 35 VIN–A AVDD 3 34 AVDD AVDD 4 33 PDWN CLK– 5 32 CSB AD9253-EP CLK+ 6 31 SDIO/OLM TOP VIEW AVDD 7 30 SCLK/DTP (Not to Scale) DRVDD 8 29 DRVDD D1–D 9 28 D0+A D1+D 10 27 D0–A D0–D 11 26 D1+A D0+D 12 25 D1–A 13 14 15 16 17 18 19 20 21 22 23 24 C C – + B B O– O+ D1–C D1+ D0–C D0+ DCO DCO FC FC D1–B D1+ D0–B D0+ NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.
007
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
1074- 1 Figure 2. Pin Configuration, Top View
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
0 AGND, Exposed Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the Pad analog ground for the part. This exposed pad must be connected to ground for proper operation. 1 VIN+D ADC D Analog Input True. 2 VIN−D ADC D Analog Input Complement. 3, 4, 7, 34, AVDD 1.8 V Analog Supply Pins. 39, 45, 46 5, 6 CLK−, CLK+ Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 8, 29 DRVDD Digital Output Driver Supply. 9, 10 D1−D, D1+D Channel D Digital Outputs, Disabled in One-Lane Mode1. 11, 12 D0−D, D0+D Channel D Digital Outputs, Disabled in One-Lane Mode1. 13, 14 D1−C, D1+C Channel C Digital Outputs (Channel D Digital Outputs in One-Lane Mode1). 15, 16 D0−C, D0+C Channel C Digital Outputs. 17, 18 DCO−, DCO+ Data Clock Outputs. 19, 20 FCO−, FCO+ Frame Clock Outputs. 21, 22 D1−B, D1+B Channel B Digital Outputs. 23, 24 D0−B, D0+B Channel B Digital Outputs (Channel A Digital Outputs in One-Lane Mode1). 25, 26 D1−A, D1+A Channel A Digital Outputs, Disabled in One-Lane Mode1. 27, 28 D0−A, D0+A Channel A Digital Outputs, Disabled in One-Lane Mode1. 30 SCLK/DTP SPI Clock Input/Digital Test Pattern. 31 SDIO/OLM SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode. 32 CSB SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up resistor. 33 PDWN Digital Input, 30 kΩ Internal Pull-Down Resistor. PDWN high = power-down device. PDWN low = run device, normal operation. 35 VIN−A ADC A Analog Input Complement. 36 VIN+A ADC A Analog Input True. 37 VIN+B ADC B Analog Input True. 38 VIN−B ADC B Analog Input Complement. 40 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 41 SENSE Reference Mode Selection. Rev. B | Page 8 of 11 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide