Datasheet AD9253-EP (Analog Devices)

Quad, 14-Bit, 125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Enhanced Product AD9253-EP FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V supply operation AVDD PDWN DRVDD Military temperature range (−55°C to +125°C) 14 SERIAL D0+A VIN+A PIPELINE DIGITAL LVDS Controlled manufacturing baseline D0–A VIN–A ADC SERIALIZER SERIAL D1+A Qualification data available on request LVDS 14 D1–A VIN+B Low power: 110 mW per channel at 125 MSPS PIPELINE DIGITAL SERIAL D0+B VIN–B ADC SERIALIZER LVDS D0–B SNR = 74 dB (to Nyquist) RBIAS SERIAL D1+B SFDR = 90 dBc (to Nyquist) VREF LVDS D1–B SENSE DNL = ±0.8 LSB (typical); INL = ±2.0 LSB (typical) FCO+ REF 1V AD9253-EP FCO– Serial LVDS (ANSI-644, default) and low power, reduced signal SELECT AGND D0+C SERIAL 14 LVDS option (similar to IEEE 1596.3) D0–C VIN+C PIPELINE DIGITAL D1+C SERIAL 650 MHz full power analog bandwidth VIN–C ADC SERIALIZER LVDS D1–C 2 V p-p input voltage range 14 SERIAL D0+D VIN+D DIGITAL LVDS D0–D PIPELINE Serial port control VIN–D ADC SERIALIZER SERIAL D1+D Full chip and individual channel power-down modes LVDS D1–D SERIAL PORT Flexible bit orientation CLOCK DCO+ VCM INTERFACE MANAGEMENT DCO– Built-in and custom digital test pattern generation Multichip sync and clock divider B C + – LM TP K K Programmable output clock and data alignment CS /O /D SYN CL CL
001
IO LK
4-
Programmable output resolution C SD S
107 1
Standby mode
Figure 1.
APPLICATIONS
designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test
Medical ultrasound
pattern generation. The available digital test patterns include
High speed imaging
built-in deterministic and pseudorandom patterns, along with
Quadrature radio receivers
custom user-defined test patterns entered via the serial port
Diversity radio receivers
interface (SPI).
Test equipment
The AD9253-EP is available in a RoHS-compliant, 48-lead LFCSP
GENERAL DESCRIPTION
and is specified over an extended temperature range of −55°C to The AD9253-EP is a quad, 14-bit, 125 MSPS analog-to-digital +125°C. This product is protected by a U.S. patent. Additional converter (ADC) with an on-chip, sample-and-hold circuit application and technical information can be found in the AD9253 designed for low cost, low power, small size, and ease of use. data sheet. The product operates at a conversion rate of up to 125 MSPS
PRODUCT HIGHLIGHTS
and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. 1. Small Footprint. Four ADCs are contained in a small, space- saving package. The ADC requires a single 1.8 V power supply and LVPECL-/ 2. Low power of 110 mW/channel at 125 MSPS with scalable CMOS-/LVDS-compatible sample rate clock for full performance power options. operation. No external reference or driver components are required 3. Ease of Use. A DCO operates at frequencies of up to 500 MHz for many applications. and supports double data rate (DDR) operation. The ADC automatically multiplies the sample rate clock for the 4. User Flexibility. The SPI control offers a wide range of appropriate LVDS serial data rate. A data clock output (DCO) for flexible features to meet specific system requirements. capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide