Datasheet AD9671 (Analog Devices) - 7

Data Sheet AD9671 Parameter1 Test Conditions/Comments Min Typ Max Unit
ADC Resolution 14 Bits SNR 75 dB ADC REFERENCE Output Voltage Error VREF = 1 V ±50 mV Load Regulation at 1.0 mA VREF = 1 V 2 mV Input Resistance 7.5 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The overrange condition is specified as 6 dB more than the full-scale input range. 3 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be 4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly. 4 Baseband decimation rate = 4. M = 16. Rev. A| Page 7 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control DIGITAL OUTPUTS AND TIMING JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Verify FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Super Frame and Output Zero Stuffing Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins ANALOG TEST TONE GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Update (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE