Datasheet AD9675 (Analog Devices) - 10

AD9675 Data Sheet Parameter1 Temperature Min Typ Max Unit
LO GENERATION MLO± Frequency 4LO Mode Full 4 40 MHz 8LO Mode Full 8 80 MHz 16LO Mode Full 16 160 MHz RESET± to MLO± Setup Time (tSETUP) Full 1 tMLO/2 ns RESET± to MLO± Hold Time (tHOLD) Full 1 tMLO/2 ns 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Can be adjusted via the SPI. 3 Mode III must have the RF decimator enabled. 4 Mode IV must have the RF decimator enabled. 5 PLL lock time from 0 Hz to 40 MHz frequency change. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode.
CLK±, TX_TRIG± Synchronization Timing Diagram tSETUP tHOLD TX_TRIG+ TX_TRIG– tEH tEL CLK–
-002
CLK+
1381 1 Figure 2. TX_TRIG± to CLK± Input Timing
CW Timing Diagram tMLO MLO– MLO+ tHOLD tSETUP RESET– RESET+
004 1381- 1 Figure 3. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 4LO Mode
tMLO MLO– MLO+ tHOLD tSETUP RESET–
-005
RESET+
1381 1 Figure 4. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 8LO Mode Rev. A | Page 10 of 60 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications AC Specifications Digital Specifications Switching Specifications CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Theory of Operation TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins Analog Test Tone Generation CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Digital RF Decimator Vector Profile RF Decimator DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter Digital Test Waveforms Waveform Generator Channel ID and Ramp Generator Digital Block Power Saving Scheme Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Recommended Start-Up Sequence Memory Map Register Table Memory Map Register Descriptions Transfer (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) Outline Dimensions Ordering Guide