Datasheet AD9697 (Analog Devices) - 9

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Data Sheet AD9697 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
CLK+ TO SYSREF+ TIMING REQUIREMENTS See Figure 3 tSU_SR Device clock to SYSREF+ setup time −70 ps tH_SR Device clock to SYSREF+ hold time 120 ps SPI TIMING REQUIREMENTS See Figure 4 tDS Setup time between the data and the rising edge of SCLK 4 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns tLOW Minimum period that SCLK must be in a logic low state 10 ns tACCESS Maximum time delay between falling edge of SCLK and output 6 10 ns data valid for a read operation tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the CSB rising edge (not shown in Figure 4)
Timing Diagrams APERTURE DELAY ANALOG INPUT N + 1 SIGNAL N – 74 N – 75 N – 73 SAMPLE N N – 72 N – 1 CLK– CLK+ CLK– CLK+ SERDOUT0– CONVERTER0 A B C D E F G H I J SAMPLE N – 74 MSB SERDOUT0+ SERDOUT1– CONVERTER0 A B C D E F G H I J SAMPLE N – 75 LSB SERDOUT1+ SERDOUT2– CONVERTER0 A B C D E F G H I J SAMPLE N – 73 MSB SERDOUT2+ SERDOUT3– CONVERTER0 A B C D E F G H I J SAMPLE N – 72 LSB SERDOUT3+ SAMPLE N – 75 AND N – 74
002
ENCODED INTO ONE 8-BIT/10-BIT SYMBOL
16253- Figure 2. Data Output Timing Diagram
CLK– CLK+ tSU_SR tH_SR SYSREF–
3 0 -0
SYSREF+
253 16 Figure 3. SYSREF± Setup and Hold Timing Diagram Rev. 0 | Page 9 of 130 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Absolute Maximum Input Swing Dither VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) SETTING UP THE AD9697 DIGITAL INTERFACE Example Setup 1—Full Bandwidth Mode Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels SPI Soft Reset MEMORY MAP REGISTERS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE