Datasheet AD4110-1 (Analog Devices) - 8

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AD4110-1 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
Input Leakage Current −10 +10 µA Pin Capacitance 12 pF Duty Cycle, Internal Clock 50 % POWER REQUIREMENTS See the Power Supply Sequence section VDD − VSS Voltage 24 30 40 V AGND Voltage (VDD − VSS)/2 V AVDD5 − AGND Voltage 4.5 5 5.5 V DGND Voltage AGND V IOVDD − DGND Voltage 2.0 5 5.5 V VDD Supply Current Field Power Supply Off 5.5 8 mA All current sources off and disabled 7.5 10 mA RTD current sources on, other current sources off, VBIAS off Field Power Supply On2 29.5 mA Field power supply current = 24 mA to AGND, all current sources off and disabled, VBIAS off VSS Supply Current Field Power Supply Off −5.5 −8 mA All current sources off and disabled −5.5 −10 mA RTD current sources on, other current sources off, VBIAS off Field Power Supply On2 −5.8 mA Field power supply current = 24 mA to AGND, all current sources off and disabled, VBIAS off AVDD5 Supply Current 10 12 mA IOVDD Supply Current 2.5 3.5 mA 1 The device is specified to operate with an input voltage from VSS + 3 V to VDD − 3 V on any AIN(±) pin. The device is protected against overvoltage on the AIN(+) and AIN(−) pins up to ±30 V (referred to the AGND supply). The limitation of VDD = VSS ≤ ± 15 V only applies when field power supply mode is enabled. Applying a voltage to a high voltage pin that is more negative than the potential of the system negative power supply can only be accomplished by connecting an external diode from the VSS pin to the system negative power supply (see Figure 29). The absolute maximum ratings must not be exceeded at any time (see Table 3). 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Gain error prior to applying software error correction algorithm. See the Gain Calibration Data Register section. 4 Gain error after applying software error correction algorithm. See the Gain Calibration Application Examples section. 5 Data based on the following test methods: - Moisture/Reflow Sensitivity (MSL) Classification for nonhermetic Solid State Surface Mount Devices and High Temperature Operating Life (HTOL). 6 Offset voltage seen at the inputs in voltage mode. Note that RTD currents can cause an additional I × R offset voltage (±V) due to any mismatch in IC or PCB trace resistance. System calibration may be required when changing RTD excitation and compensation current levels. 7 DC input impedance is derived from measuring the change in input current for a change in input voltage, (ΔVIN ÷ ΔIIN). 8 Referred to input. 9 PGA gain = 4 for all specifications related to the current input mode with internal sense resistor. 10 Input current in current input mode must be within ±20 mA for fully specified performance. The device is functional up to ±24 mA. The internal protection limits the input overcurrent to approximately 40 mA. 11 Current mode input impedance is the total impedance between the AIN(+) and AIN(−) pins, which includes the on-chip sense resistor, on-chip current mode switches, and other on-chip circuits. The relationship between the analog input current and the analog output voltage is represented by the gain and offset specifications. 12 REXT = 200 Ω and gain = 0.5 for all specifications related to the current input mode with external sense resistor. 13 The external resistor transfers the input current to a voltage for additional signal processing in this mode. The AD4110-1 specifications exclude the effect of any changes in the external resistor resistance. Performance of the external resistor must be considered to assess system performance in this mode. 14 The AD4110-1 RTD excitation currents are designed to operate with a 2.5 V reference voltage. The AD4110-1 RTD excitation current value scales proportionally to small changes in the VREF input voltage. The AD4110-1 RTD excitation current specifications exclude the effect of any changes in the VREF input voltage. 15 RTD current source enabled and current flowing continuously. 16 This specification relates to the worst high voltage and low voltage channel pair. A 20 V p-p, 1 kHz sine wave input on the HV channel is attenuated by this amount on the other LV channels. The interferer signal is applied to an unselected channel. The filter network connected to C(+) and C(−) is implemented as shown in Figure 29. There is no filter network implemented on the input terminals. Rev. 0 | Page 8 of 74 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SUPPLY SEQUENCE PROTECTION DIODE ANALOG INPUT PULL-UP/PULL-DOWN CURRENTS ANTIALIASING FILTER RTD EXCITATION CURRENTS FIELD POWER SUPPLY MODE NO POWER SUPPLY MODE BIAS VOLTAGE GENERATOR PGA CALIBRATION REGISTERS SERIAL INTERFACE CLOCK ADC ADC FILTER REGISTERS ADC GAIN AND OFFSET REGISTERS NOISE PERFORMANCE AND RESOLUTION MODES OF OPERATION DEFAULT MODE OF OPERATION ON POWER-UP CHANGING THE DEFAULT MODE OF OPERATION FOR FUTURE POWER-UP CYCLES POWER SUPPLY REQUIREMENTS SYSTEM CLOCK REQUIREMENTS BIPOLAR AND UNIPOLAR OUTPUT AUXILIARY LOW VOLTAGE INPUTS DIGITAL FILTER CONTINUOUS CONVERSION MODE INPUT AUTO SEQUENCING SINGLE CONVERSION MODE ADC CONVERSION DELAY BIAS VOLTAGE GENERATOR ANTIALIASING FILTER CIRCUIT CURRENT MODE Transimpedance Gain Using an External Sense Resistor VOLTAGE AND THERMOCOUPLE MODE Input Scaling for Voltage Mode Thermocouple Inputs RTD MODE Generating RTD Currents with an External Resistor Excitation Currents RTD Initial Drift 4-Wire RTD 3-Wire RTD 2-Wire RTD Alternative 3-Wire Configuration FIELD POWER SUPPLY MODE Overvoltage Protection NO POWER SUPPLY MODE Voltage Mode Current Mode System Redundancy GAIN CALIBRATION DATA REGISTER GAIN CALIBRATION IN VOLTAGE MODE GAIN CALIBRATION IN CURRENT MODE SCALING FACTOR AUTOCALIBRATION MODES APPLICATION EXAMPLES Example 1 Example 2 DIAGNOSTICS AND PROTECTION DIAGNOSTIC FLAGS ERROR PIN OVERTEMPERATURE DETECTION AND THERMAL SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DETECTION OVERVOLTAGE PROTECTION DIAGNOSING OVERVOLTAGE AND UNDERVOLTAGE CONDITIONS OPEN WIRE DETECTION DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS RTD MODE NOISE PERFORMANCE SERIAL PERIPHERAL INTERFACE RESETTING THE AD4110-1 SPI COMMAND TO COMMUNICATIONS REGISTER DOUT/ PIN WRITE OPERATION READ OPERATION MULTIPLE DEVICES ON THE SPI BUS CRC CHECKSUM CRC CHECKSUM METHODS Polynomial Calculation Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation REGISTER DETAILS AFE REGISTER MAP AFE REGISTER DESCRIPTIONS AFE_TOP_STATUS Register AFE_CNTRL1 Register AFE_CLK_CTRL Register AFE_CNTRL2 Register PGA_RTD_CTRL Register AFE_ERR_DISABLE Register AFE_DETAIL_STATUS Register AFE_CAL_DATA Register AFE_RSENSE_DATA Register NO_PWR_DEFAULT_SEL Register NO_PWR_DEFAULT_STATUS Register ADC REGISTER MAP ADC REGISTER DESCRIPTIONS ADC_STATUS Register ADC_MODE Register ADC_INTERFACE Register ADC_CONFIG Register Data Register Filter Register ADC_GPIO_CONFIG Register ID Register ADC_OFFSET0 Register ADC_OFFSET1 Register ADC_OFFSET2 Register ADC_OFFSET3 Register ADC_GAIN0 Register ADC_GAIN1 Register ADC_GAIN2 Register ADC_GAIN3 Register OUTLINE DIMENSIONS ORDERING GUIDE