Datasheet AD4110-1 (Analog Devices) - 7

FabricanteAnalog Devices
DescripciónUniversal Input Analog Front End with 24-Bit ADC for Industrial Process Control Systems
Páginas / Página74 / 7 — Data Sheet. AD4110-1. Parameter Min. Typ. Max. Unit. Test. …
Formato / tamaño de archivoPDF / 1.4 Mb
Idioma del documentoInglés

Data Sheet. AD4110-1. Parameter Min. Typ. Max. Unit. Test. Conditions/Comments

Data Sheet AD4110-1 Parameter Min Typ Max Unit Test Conditions/Comments

Línea de modelo para esta hoja de datos

Versión de texto del documento

link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8
Data Sheet AD4110-1 Parameter Min Typ Max Unit Test Conditions/Comments
INPUT OVERVOLTAGE DETECTION Positive Overvoltage Threshold VDD − 2.0 VDD − 2.8 V Negative Overvoltage Threshold VSS + 2.0 VSS + 2.8 V OVERTEMPERATURE PROTECTION Overtemperature Detection 120 °C Junction temperature Threshold Thermal Shutdown Threshold 145 °C Junction temperature Thermal Shutdown Hysteresis 30 °C ANTIALIASING FILTER RESISTOR AIN(±) to C(±) Resistance 1600 Ω Includes internal switch resistance Resistance Variation2 ±35 % Mismatch 0.2 % Resistor pair per channel LOW VOLTAGE ANALOG INPUTS, AIN1(LV), AIN2(LV), AND AINCOM(LV) Differential Input Range ±VREF V Absolute Voltage Limit AGND AVDD5 V Input Current ±65 nA Input Current Drift ±75 pA/°C AGND + 0.2 V to AVDD5 – 0.2 V ±1 nA/°C AGND to AVDD5 High Voltage (HV) to Low Voltage −120 dB Input frequency (fIN) = 1 kHz, Gain (HV (LV) Channel Crosstalk16 Channel) = 1 Input Common-Mode Rejection, DC 95 dB Input Common-Mode Rejection, AC 120 dB 50 Hz/60 Hz, VIN = 1 V DIGITAL INPUTS Input High Voltage, V 2 IH 0.7 × IOVDD V IOVDD = 2 V to 5.5 V Input Low Voltage, V 2 IL 0.8 V IOVDD = 3.3 V to 5.5 V 0.4 V IOVDD = 2 V Hysteresis 100 mV Input Leakage Current −10 +10 μA Input Pin Capacitance 10 pF DIGITAL OUTPUTS V 2 OH 0.8 × IOVDD V IOVDD = 5 V, source current (ISOURCE) = 1 mA 0.8 × IOVDD V IOVDD = 3.3 V, ISOURCE = 500 μA 0.8 × IOVDD V IOVDD = 2 V, ISOURCE = 500 μA V 2 OL 0.4 V IOVDD = 5 V, sink current (ISINK) = 2 mA 0.4 V IOVDD = 3.3 V, ISINK = 1 mA 0.4 V IOVDD = 2 V, ISINK = 1 mA Floating State Leakage Current −10 +10 μA Floating State Output Capacitance 12 pF ERROR OUTPUT (OPEN DRAIN) Output Low Voltage, VOL 0.4 V ISINK = −100 μA Output High Leakage Current, IOH −10 +10 μA Output voltage (VOUT) = 5 V CLOCK INPUT/OUTPUT Internal Oscillator 8 MHz Internal Oscillator Accuracy −3.5 +3.5 % ADC clock Clock Input Frequency 8 MHz Duty Cycle, External Clock2 45 50 55 % V 2 IH 0.8 × IOVDD V VOH 0.8 × IOVDD V VOL 0.4 V V 2 IL 0.4 V Rev. 0 | Page 7 of 74 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SUPPLY SEQUENCE PROTECTION DIODE ANALOG INPUT PULL-UP/PULL-DOWN CURRENTS ANTIALIASING FILTER RTD EXCITATION CURRENTS FIELD POWER SUPPLY MODE NO POWER SUPPLY MODE BIAS VOLTAGE GENERATOR PGA CALIBRATION REGISTERS SERIAL INTERFACE CLOCK ADC ADC FILTER REGISTERS ADC GAIN AND OFFSET REGISTERS NOISE PERFORMANCE AND RESOLUTION MODES OF OPERATION DEFAULT MODE OF OPERATION ON POWER-UP CHANGING THE DEFAULT MODE OF OPERATION FOR FUTURE POWER-UP CYCLES POWER SUPPLY REQUIREMENTS SYSTEM CLOCK REQUIREMENTS BIPOLAR AND UNIPOLAR OUTPUT AUXILIARY LOW VOLTAGE INPUTS DIGITAL FILTER CONTINUOUS CONVERSION MODE INPUT AUTO SEQUENCING SINGLE CONVERSION MODE ADC CONVERSION DELAY BIAS VOLTAGE GENERATOR ANTIALIASING FILTER CIRCUIT CURRENT MODE Transimpedance Gain Using an External Sense Resistor VOLTAGE AND THERMOCOUPLE MODE Input Scaling for Voltage Mode Thermocouple Inputs RTD MODE Generating RTD Currents with an External Resistor Excitation Currents RTD Initial Drift 4-Wire RTD 3-Wire RTD 2-Wire RTD Alternative 3-Wire Configuration FIELD POWER SUPPLY MODE Overvoltage Protection NO POWER SUPPLY MODE Voltage Mode Current Mode System Redundancy GAIN CALIBRATION DATA REGISTER GAIN CALIBRATION IN VOLTAGE MODE GAIN CALIBRATION IN CURRENT MODE SCALING FACTOR AUTOCALIBRATION MODES APPLICATION EXAMPLES Example 1 Example 2 DIAGNOSTICS AND PROTECTION DIAGNOSTIC FLAGS ERROR PIN OVERTEMPERATURE DETECTION AND THERMAL SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DETECTION OVERVOLTAGE PROTECTION DIAGNOSING OVERVOLTAGE AND UNDERVOLTAGE CONDITIONS OPEN WIRE DETECTION DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS RTD MODE NOISE PERFORMANCE SERIAL PERIPHERAL INTERFACE RESETTING THE AD4110-1 SPI COMMAND TO COMMUNICATIONS REGISTER DOUT/ PIN WRITE OPERATION READ OPERATION MULTIPLE DEVICES ON THE SPI BUS CRC CHECKSUM CRC CHECKSUM METHODS Polynomial Calculation Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation REGISTER DETAILS AFE REGISTER MAP AFE REGISTER DESCRIPTIONS AFE_TOP_STATUS Register AFE_CNTRL1 Register AFE_CLK_CTRL Register AFE_CNTRL2 Register PGA_RTD_CTRL Register AFE_ERR_DISABLE Register AFE_DETAIL_STATUS Register AFE_CAL_DATA Register AFE_RSENSE_DATA Register NO_PWR_DEFAULT_SEL Register NO_PWR_DEFAULT_STATUS Register ADC REGISTER MAP ADC REGISTER DESCRIPTIONS ADC_STATUS Register ADC_MODE Register ADC_INTERFACE Register ADC_CONFIG Register Data Register Filter Register ADC_GPIO_CONFIG Register ID Register ADC_OFFSET0 Register ADC_OFFSET1 Register ADC_OFFSET2 Register ADC_OFFSET3 Register ADC_GAIN0 Register ADC_GAIN1 Register ADC_GAIN2 Register ADC_GAIN3 Register OUTLINE DIMENSIONS ORDERING GUIDE