Datasheet AD4110-1 (Analog Devices) - 45

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Data Sheet AD4110-1 NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC3 FILTER
The AD4110-1 has three flexible filter options to allow the The sinc3 filter achieves the best single-channel noise performance optimization of noise, settling time, and rejection. at lower output data rates and is, therefore, most suitable for single-channel applications. The settling time of the sinc3 filter Sinc5 + sinc1 filter is equal to Sinc3 filter Enhanced rejection filters for 50 Hz and 60 Hz tSETTLE = 3/Output Data Rate Figure 58 shows the frequency domain response for the sinc3
50Hz AND 60Hz
filter at a 50 SPS output data rate. The sinc3 filter has good roll-
sinc5 sinc1 POST FILTER
off over frequency and wide notches for good notch frequency rejection. Selecting the sinc3 filter as the response of the AD4110-1 6
sinc3
-05 digital filter in the ADC filter register (Address 0x5) gives 100 dB 69 162 rejection of 50 Hz or 60 Hz (±1 Hz). Figure 56. Digital Filter Block Diagram Table 18 and Table 19 provide the output data rates, settling The filter and output data rate are configured by setting the times, peak-to-peak noise, and rms noise for the sinc3 filter. appropriate bits in the filter configuration register for the
0
selected channels. For more information, see the Filter Register
–10
section.
–20 SINC5 + SINC1 FILTER –30 ) –40
The sinc5 + sinc1 filter is targeted at fast switching multiplexed
(dB –50
applications and achieves single cycle settling at output data rates
IN A –60
of 10 kSPS and lower. The sinc5 block output is fixed at the maxi-
G R –70
mum rate of 125 kSPS.
TE FIL –80
Selecting the fast settling filter (sinc1) as the response of the
–90
AD4110-1 digital filter in the ADC filter register (Address 0x5)
–100
gives 40 dB rejection of 50 Hz or 60 Hz (±0.5 Hz).
–110
Figure 57 shows the frequency domain response of the sinc5 +
–120 0 50 100 150
058 sinc1 filter at a 50 SPS output data rate. The sinc5 + sinc1 filter
FREQUENCY (Hz)
6269- 1 has slow roll-off over frequency and narrow notches. Figure 58. Sinc3 Filter Response, Output Data Rate = 50 SPS
0 –20 ) B –40 (d IN GA –60 R E T FIL –80 –100 –120 0 50 100 150
057
FREQUENCY (Hz)
6269- 1 Figure 57. Sinc5 + Sinc1 Filter Response, Output Data Rate = 50 SPS Table 16 and Table 17 provide the output data rates, settling times, peak-to-peak noise, and rms noise for the sinc5 + sinc1 filter. Rev. 0 | Page 45 of 74 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SUPPLY SEQUENCE PROTECTION DIODE ANALOG INPUT PULL-UP/PULL-DOWN CURRENTS ANTIALIASING FILTER RTD EXCITATION CURRENTS FIELD POWER SUPPLY MODE NO POWER SUPPLY MODE BIAS VOLTAGE GENERATOR PGA CALIBRATION REGISTERS SERIAL INTERFACE CLOCK ADC ADC FILTER REGISTERS ADC GAIN AND OFFSET REGISTERS NOISE PERFORMANCE AND RESOLUTION MODES OF OPERATION DEFAULT MODE OF OPERATION ON POWER-UP CHANGING THE DEFAULT MODE OF OPERATION FOR FUTURE POWER-UP CYCLES POWER SUPPLY REQUIREMENTS SYSTEM CLOCK REQUIREMENTS BIPOLAR AND UNIPOLAR OUTPUT AUXILIARY LOW VOLTAGE INPUTS DIGITAL FILTER CONTINUOUS CONVERSION MODE INPUT AUTO SEQUENCING SINGLE CONVERSION MODE ADC CONVERSION DELAY BIAS VOLTAGE GENERATOR ANTIALIASING FILTER CIRCUIT CURRENT MODE Transimpedance Gain Using an External Sense Resistor VOLTAGE AND THERMOCOUPLE MODE Input Scaling for Voltage Mode Thermocouple Inputs RTD MODE Generating RTD Currents with an External Resistor Excitation Currents RTD Initial Drift 4-Wire RTD 3-Wire RTD 2-Wire RTD Alternative 3-Wire Configuration FIELD POWER SUPPLY MODE Overvoltage Protection NO POWER SUPPLY MODE Voltage Mode Current Mode System Redundancy GAIN CALIBRATION DATA REGISTER GAIN CALIBRATION IN VOLTAGE MODE GAIN CALIBRATION IN CURRENT MODE SCALING FACTOR AUTOCALIBRATION MODES APPLICATION EXAMPLES Example 1 Example 2 DIAGNOSTICS AND PROTECTION DIAGNOSTIC FLAGS ERROR PIN OVERTEMPERATURE DETECTION AND THERMAL SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DETECTION OVERVOLTAGE PROTECTION DIAGNOSING OVERVOLTAGE AND UNDERVOLTAGE CONDITIONS OPEN WIRE DETECTION DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS RTD MODE NOISE PERFORMANCE SERIAL PERIPHERAL INTERFACE RESETTING THE AD4110-1 SPI COMMAND TO COMMUNICATIONS REGISTER DOUT/ PIN WRITE OPERATION READ OPERATION MULTIPLE DEVICES ON THE SPI BUS CRC CHECKSUM CRC CHECKSUM METHODS Polynomial Calculation Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation REGISTER DETAILS AFE REGISTER MAP AFE REGISTER DESCRIPTIONS AFE_TOP_STATUS Register AFE_CNTRL1 Register AFE_CLK_CTRL Register AFE_CNTRL2 Register PGA_RTD_CTRL Register AFE_ERR_DISABLE Register AFE_DETAIL_STATUS Register AFE_CAL_DATA Register AFE_RSENSE_DATA Register NO_PWR_DEFAULT_SEL Register NO_PWR_DEFAULT_STATUS Register ADC REGISTER MAP ADC REGISTER DESCRIPTIONS ADC_STATUS Register ADC_MODE Register ADC_INTERFACE Register ADC_CONFIG Register Data Register Filter Register ADC_GPIO_CONFIG Register ID Register ADC_OFFSET0 Register ADC_OFFSET1 Register ADC_OFFSET2 Register ADC_OFFSET3 Register ADC_GAIN0 Register ADC_GAIN1 Register ADC_GAIN2 Register ADC_GAIN3 Register OUTLINE DIMENSIONS ORDERING GUIDE