Datasheet AD7327-EP (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 500 kSPS, 8-Channel, Software Selectable True bipolar Input, 12-Bit Plus Sign A/D Converter |
| Páginas / Página | 14 / 7 — Enhanced Product. AD7327-EP. TIMING SPECIFICATIONS. Table 2. Limit at … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 401 Kb |
| Idioma del documento | Inglés |
Enhanced Product. AD7327-EP. TIMING SPECIFICATIONS. Table 2. Limit at TMIN, TMAX. Description. Parameter. VCC < 4.75 V
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Enhanced Product AD7327-EP TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external, TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Limit at TMIN, TMAX Description Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit VDRIVE ≤ VCC
fSCLK 50 50 kHz min 10 10 MHz max tCONVERT 16 × tSCLK 16 × tSCLK ns max tSCLK = 1/fSCLK tQUIET 75 60 ns min Minimum time between end of serial read and next fal ing edge of CS t1 12 5 ns min Minimum CS pulse width t 1 2 25 20 ns min CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V) 45 35 ns min Unipolar input range (0 V to 10 V) t3 26 14 ns max Delay from CS until DOUT three-state disabled t4 57 43 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 13 8 ns min SCLK to data valid hold time t8 40 22 ns max SCLK falling edge to DOUT high impedance 10 9 ns min SCLK falling edge to DOUT high impedance t9 4 4 ns min DIN set-up time prior to SCLK falling edge t10 2 2 ns min DIN hold time after SCLK falling edge tPOWER-UP 750 750 ns max Power-up from autostandby 500 500 µs max Power-up from full shutdown/autoshutdown mode, internal reference 25 25 µs typ Power-up from full shutdown/autoshutdown mode, external reference 1 When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.
t1 CS tCONVERT t2 t6 SCLK 1 2 3 4 5 13 14 15 16 3 IDENTIFICATION BITS t t 7 5 t t t 8 4 3 tQUIET DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0 THREE- ADD2 t THREE-STATE STATE t 10 9 REG REG DON’T
002
WRITE MSB LSB DIN SEL1 SEL2 CARE
12481- Figure 2. Serial Interface Timing Diagram Rev. C | Page 7 of 14 Document Outline FEATURES ENHANCED PRODUCT FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external, TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Limit at TMIN, TMAX Description Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit VDRIVE ≤ VCC
fSCLK 50 50 kHz min 10 10 MHz max tCONVERT 16 × tSCLK 16 × tSCLK ns max tSCLK = 1/fSCLK tQUIET 75 60 ns min Minimum time between end of serial read and next fal ing edge of CS t1 12 5 ns min Minimum CS pulse width t 1 2 25 20 ns min CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V) 45 35 ns min Unipolar input range (0 V to 10 V) t3 26 14 ns max Delay from CS until DOUT three-state disabled t4 57 43 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 13 8 ns min SCLK to data valid hold time t8 40 22 ns max SCLK falling edge to DOUT high impedance 10 9 ns min SCLK falling edge to DOUT high impedance t9 4 4 ns min DIN set-up time prior to SCLK falling edge t10 2 2 ns min DIN hold time after SCLK falling edge tPOWER-UP 750 750 ns max Power-up from autostandby 500 500 µs max Power-up from full shutdown/autoshutdown mode, internal reference 25 25 µs typ Power-up from full shutdown/autoshutdown mode, external reference 1 When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.
t1 CS tCONVERT t2 t6 SCLK 1 2 3 4 5 13 14 15 16 3 IDENTIFICATION BITS t t 7 5 t t t 8 4 3 tQUIET DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0 THREE- ADD2 t THREE-STATE STATE t 10 9 REG REG DON’T
002
WRITE MSB LSB DIN SEL1 SEL2 CARE
12481- Figure 2. Serial Interface Timing Diagram Rev. C | Page 7 of 14 Document Outline FEATURES ENHANCED PRODUCT FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE