Enhanced ProductAD7327-EPPIN CONFIGURATION AND FUNCTION DESCRIPTIONSCS 120SCLKDIN 219DGNDDGND 318DOUTAD7327-EPAGND 417TOP VIEWVDRIVE(Not to Scale)REFIN/OUT 516VCCV615SSVDDV714IN0VIN2V813IN1VIN3V912IN4VIN6 003 V1011IN5VIN7 12481- Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.Mnemonic Description 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7327-EP and frames the serial data transfer. 2 DIN Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the AD7327-EP on the falling edge of SCLK (see the Registers section of AD7327 data sheet). 3, 19 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7327-EP. The DGND and AGND voltages, ideally, share the same potential and must not be more than 0.3 V apart, even on a transient basis. 4 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7327-EP. Refer all analog input signals and any external reference signal to this AGND voltage. The AGND and DGND voltages, ideally, share the same potential and must not be more than 0.3 V apart, even on a transient basis. 5 REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the AD7327-EP. The nominal internal reference voltage is 2.5 V, which appears at this pin. Place a 680 nF capacitor on the reference pin (see the Reference section of the AD7327 data sheet). Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default condition. 6 VSS Negative Power Supply Voltage. VSS is the negative supply voltage for the analog input section. 7 to 14 VIN0 to VIN7 Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input channel for conversion is selected by programming the Channel Address Bit ADD2 through Channel Address Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is controlled by programming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input channel when a +2.5 V reference voltage is used (see the Registers section of AD7327 data sheet). 15 VDD Positive Power Supply Voltage. VDD is the positive supply voltage for the analog input section. 16 VCC Analog Supply Voltage, 2.7 V to 5.25 V. VCC is the supply voltage for the ADC core on the AD7327-EP. Decouple this supply to AGND. 17 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. Decouple this pin to DGND. The voltage at this pin may be different to that at VCC, but VDRIVE must not exceed VCC by more than 0.3 V. 18 DOUT Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the Serial Interface section of AD7327 data sheet). 20 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7327-EP. This clock is also used as the clock source for the conversion process. Rev. C | Page 9 of 14 Document Outline FEATURES ENHANCED PRODUCT FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE